diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2022-09-29 15:33:15 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2023-01-16 09:26:05 +0100 |
| commit | 61b7f8920b176e3cb86c3b5e7c866261720a7917 (patch) | |
| tree | 5c02c69a09fdd701ceea6b3bf538b28cac989ad7 /arch/arm/mach-s3c/regs-mem-s3c24xx.h | |
| parent | 1027b4df8354c55a5ed538e391d4cf9c509b74a7 (diff) | |
ARM: s3c: remove all s3c24xx support
The platform was deprecated in commit 6a5e69c7ddea ("ARM: s3c: mark
as deprecated and schedule removal") and can be removed. This includes
all files that are exclusively for s3c24xx and not shared with s3c64xx,
as well as the glue logic in Kconfig and the maintainer file entries.
Cc: Arnaud Patard <arnaud.patard@rtp-net.org>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Christer Weinigel <christer@weinigel.se>
Cc: Guillaume GOURAT <guillaume.gourat@nexvision.tv>
Cc: Heiko Stuebner <heiko@sntech.de>
Cc: Simtec Linux Team <linux@simtec.co.uk>
Cc: openmoko-kernel@lists.openmoko.org
Acked-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-s3c/regs-mem-s3c24xx.h')
| -rw-r--r-- | arch/arm/mach-s3c/regs-mem-s3c24xx.h | 53 |
1 files changed, 0 insertions, 53 deletions
diff --git a/arch/arm/mach-s3c/regs-mem-s3c24xx.h b/arch/arm/mach-s3c/regs-mem-s3c24xx.h deleted file mode 100644 index 8fed34a1672a..000000000000 --- a/arch/arm/mach-s3c/regs-mem-s3c24xx.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk> - * http://www.simtec.co.uk/products/SWLINUX/ - * - * S3C2410 Memory Control register definitions - */ - -#ifndef __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H -#define __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H __FILE__ - -#include "map-s3c.h" - -#define S3C2410_MEMREG(x) (S3C24XX_VA_MEMCTRL + (x)) - -#define S3C2410_BWSCON S3C2410_MEMREG(0x00) -#define S3C2410_BANKCON0 S3C2410_MEMREG(0x04) -#define S3C2410_BANKCON1 S3C2410_MEMREG(0x08) -#define S3C2410_BANKCON2 S3C2410_MEMREG(0x0C) -#define S3C2410_BANKCON3 S3C2410_MEMREG(0x10) -#define S3C2410_BANKCON4 S3C2410_MEMREG(0x14) -#define S3C2410_BANKCON5 S3C2410_MEMREG(0x18) -#define S3C2410_BANKCON6 S3C2410_MEMREG(0x1C) -#define S3C2410_BANKCON7 S3C2410_MEMREG(0x20) -#define S3C2410_REFRESH S3C2410_MEMREG(0x24) -#define S3C2410_BANKSIZE S3C2410_MEMREG(0x28) - -#define S3C2410_BWSCON_ST1 (1 << 7) -#define S3C2410_BWSCON_ST2 (1 << 11) -#define S3C2410_BWSCON_ST3 (1 << 15) -#define S3C2410_BWSCON_ST4 (1 << 19) -#define S3C2410_BWSCON_ST5 (1 << 23) - -#define S3C2410_BWSCON_GET(_bwscon, _bank) (((_bwscon) >> ((_bank) * 4)) & 0xf) - -#define S3C2410_BWSCON_WS (1 << 2) - -#define S3C2410_BANKCON_PMC16 (0x3) - -#define S3C2410_BANKCON_Tacp_SHIFT (2) -#define S3C2410_BANKCON_Tcah_SHIFT (4) -#define S3C2410_BANKCON_Tcoh_SHIFT (6) -#define S3C2410_BANKCON_Tacc_SHIFT (8) -#define S3C2410_BANKCON_Tcos_SHIFT (11) -#define S3C2410_BANKCON_Tacs_SHIFT (13) - -#define S3C2410_BANKCON_SDRAM (0x3 << 15) - -#define S3C2410_REFRESH_SELF (1 << 22) - -#define S3C2410_BANKSIZE_MASK (0x7 << 0) - -#endif /* __ARCH_ARM_MACH_S3C24XX_REGS_MEM_H */ |