diff options
| author | Jonathan Austin <jonathan.austin@arm.com> | 2016-08-30 17:31:22 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@armlinux.org.uk> | 2016-09-06 15:51:08 +0100 |
| commit | bc0ee9d24ad21a5c2b5944f66623a02e9c8831aa (patch) | |
| tree | 8bcff63e1b50e2d1c7211935092cff827867cded /arch/arm/mm/proc-v7m.S | |
| parent | 9a1af5f2206bd303ed201c6895c42ac3ac120a20 (diff) | |
ARM: 8607/1: V7M: Wire up caches for V7M processors with cache support.
This patch does the plumbing required to invoke the V7M cache code added
in earlier patches in this series, although there is no users for that
yet.
In order to honour the I/D cache disable config options, this patch changes
the mechanism by which the CCR is set on boot, to be more like V7A/R.
Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Andras Szemzo <sza@esh.hu>
Tested-by: Joachim Eastwood <manabian@gmail.com>
Tested-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/proc-v7m.S')
| -rw-r--r-- | arch/arm/mm/proc-v7m.S | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/arm/mm/proc-v7m.S b/arch/arm/mm/proc-v7m.S index 7229d8d0be1a..11f5816e2680 100644 --- a/arch/arm/mm/proc-v7m.S +++ b/arch/arm/mm/proc-v7m.S @@ -118,9 +118,8 @@ __v7m_setup: @ Configure the System Control Register to ensure 8-byte stack alignment @ Note the STKALIGN bit is either RW or RAO. - ldr r12, [r0, V7M_SCB_CCR] @ system control register - orr r12, #V7M_SCB_CCR_STKALIGN - str r12, [r0, V7M_SCB_CCR] + ldr r0, [r0, V7M_SCB_CCR] @ system control register + orr r0, #V7M_SCB_CCR_STKALIGN ret lr ENDPROC(__v7m_setup) |