diff options
| author | Michael Walle <michael@walle.cc> | 2020-11-08 19:51:05 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2020-11-30 22:30:29 +0800 |
| commit | d0570a575aa83116bd0f6a99c4de548af773d950 (patch) | |
| tree | 5ca61a438e1479217d7d7bdaf1b971bebbc0f68c /arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | |
| parent | bd5840df916dc57929af727ff99b63a93be096c6 (diff) | |
arm64: dts: ls1028a: fix ENETC PTP clock input
On the LS1028A the ENETC reference clock is connected to 4th HWA output,
see Figure 7 "Clock subsystem block diagram".
The PHC may run with a wrong frequency. ptp_qoriq_auto_config() will read
the clock speed of the clock given in the device tree. It is likely that,
on the reference board this wasn't noticed because both clocks have the
same frequency. But this must not be always the case. Fix it.
Fixes: 49401003e260 ("arm64: dts: fsl: ls1028a: add ENETC 1588 timer node")
Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index ac17752ab3ec..ae5769cf4e95 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -952,7 +952,7 @@ ethernet@0,4 { compatible = "fsl,enetc-ptp"; reg = <0x000400 0 0 0 0>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen 2 3>; little-endian; fsl,extts-fifo; }; |