diff options
| author | Hui Wang <hui.wang@canonical.com> | 2023-07-31 16:46:14 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2023-08-06 20:17:53 +0800 |
| commit | fcf7ff67a2aa6d8055b9b815ad8a28a5231afa1e (patch) | |
| tree | 6bec9a96d595dbc4b611b44d2301b9496b020cf2 /arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | |
| parent | aca26870217b14f6ccc5a4b5c9d16879756a5ed0 (diff) | |
arm64: dts: ls1028a: add l1 and l2 cache info
When we ran the stress-ng cache related stressors, we got the log as
below:
ubuntu@ubuntu:~$ stress-ng --l1cache 4
stress-ng: info: [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor
stress-ng: info: [656] dispatching hogs: 4 l1cache
stress-ng: info: [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel
This is because the l1 and l2 cache info is missing in the devicetree,
ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and
1MB l2 ucache:
- icache is 3-way set associative
- dcache is 2-way set associative
- l2cache is 16-way set associative
- line size are 64bytes
Signed-off-by: Hui Wang <hui.wang@canonical.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9cbb31191cf9..eefe3577d94e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -28,6 +28,12 @@ reg = <0x0>; enable-method = "psci"; clocks = <&clockgen QORIQ_CLK_CMUX 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -39,6 +45,12 @@ reg = <0x1>; enable-method = "psci"; clocks = <&clockgen QORIQ_CLK_CMUX 0>; + i-cache-size = <0xc000>; + i-cache-line-size = <64>; + i-cache-sets = <256>; + d-cache-size = <0x8000>; + d-cache-line-size = <64>; + d-cache-sets = <256>; next-level-cache = <&l2>; cpu-idle-states = <&CPU_PW20>; #cooling-cells = <2>; @@ -48,6 +60,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x100000>; + cache-line-size = <64>; + cache-sets = <1024>; }; }; |