diff options
| author | Leonard Crestez <leonard.crestez@nxp.com> | 2019-11-22 23:45:04 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-12-09 09:22:26 +0800 |
| commit | 0376f6ec9eb8690e8efcf37e4ae2e0a7cc0fef1d (patch) | |
| tree | 9a90b0b1ec17d748c499bb846098dbf34097676c /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
| parent | 0f93eb28ff3a348818509aac7850a8f6df114a3f (diff) | |
arm64: dts: imx8m: Add ddr controller nodes
This is used by the imx-ddrc devfreq driver to implement dynamic
frequency scaling of DRAM.
Support for proactive scaling via interconnect will come later. The
high-performance bus masters which need that (display, vpu, gpu) are
mostly not yet enabled in upstream anyway.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8mm.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index da297b5e509d..20756440a420 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -858,6 +858,16 @@ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; + ddrc: memory-controller@3d400000 { + compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; + reg = <0x3d400000 0x400000>; + clock-names = "core", "pll", "alt", "apb"; + clocks = <&clk IMX8MM_CLK_DRAM_CORE>, + <&clk IMX8MM_DRAM_PLL>, + <&clk IMX8MM_CLK_DRAM_ALT>, + <&clk IMX8MM_CLK_DRAM_APB>; + }; + ddr-pmu@3d800000 { compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu"; reg = <0x3d800000 0x400000>; |