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author | Vladimir Oltean <vladimir.oltean@nxp.com> | 2021-03-08 15:08:34 +0200 |
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committer | Shawn Guo <shawnguo@kernel.org> | 2021-03-29 09:49:57 +0800 |
commit | 2c832fe41a8d79d40bba8c5b7147ba47a1d15615 (patch) | |
tree | 1c41757db4473cc06e8ab6e576f8be246f32770d /arch/arm64/boot/dts/freescale/imx8mm.dtsi | |
parent | 4eac5e728b9d753611817bd30c14881aa950a318 (diff) |
arm64: dts: ls1028a: set up the real link speed for ENETC port 2
In NXP LS1028A there is a MAC-to-MAC internal link between enetc_port2
and mscc_felix_port4. This link operates at 2.5Gbps and is described as
such for the mscc_felix_port4 node.
The reason for the discrepancy is a limitation in the PHY library
support for fixed-link nodes. Due to the fact that the PHY library
registers a software PHY which emulates the clause 22 register map, the
drivers/net/phy/fixed_phy.c driver only supports speeds up to 1Gbps.
The mscc_felix_port4 node is probed by DSA, which does not use the PHY
library directly, but phylink, and phylink has a different representation
for fixed-link nodes, one that does not have the limitation of not being
able to represent speeds > 1Gbps.
Since the enetc driver was converted to phylink too as of commit
71b77a7a27a3 ("enetc: Migrate to PHYLINK and PCS_LYNX"), the limitation
has been practically lifted there too, and we can describe the real link
speed in the device tree now.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8mm.dtsi')
0 files changed, 0 insertions, 0 deletions