Merge tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull SoC device tree updates from Arnd Bergmann:
 "There is very little going on with new SoC support this time, all the
  new chips are variations of others that we already support, and they
  are all based on ARMv8 cores:

   - Mediatek MT7981B (Filogic 820) and MT7988A (Filogic 880) are
     networking SoCs designed to be used in wireless routers, similar to
     the already supported MT7986A (Filogic 830).

   - NXP i.MX8DXP is a variant of i.MX8QXP, with two CPU cores less.
     These are used in many embedded and industrial applications.

   - Renesas R8A779G2 (R-Car V4H ES2.0) and R8A779H0 (R-Car V4M) are
     automotive SoCs.

   - TI J722S is another automotive variant of its K3 family, related to
     the AM62 series.

  There are a total of 7 new arm32 machines and 45 arm64 ones, including

   - Two Android phones based on the old Tegra30 chip

   - Two machines using Cortex-A53 SoCs from Allwinner, a mini PC and a
     SoM development board

   - A set-top box using Amlogic Meson G12A S905X2

   - Eight embedded board using NXP i.MX6/8/9

   - Three machines using Mediatek network router chips

   - Ten Chromebooks, all based on Mediatek MT8186

   - One development board based on Mediatek MT8395 (Genio 1200)

   - Seven tablets and phones based on Qualcomm SoCs, most of them from
     Samsung.

   - A third development board for Qualcomm SM8550 (Snapdragon 8 Gen 2)

   - Three variants of the "White Hawk" board for Renesas automotive
     SoCs

   - Ten Rockchips RK35xx based machines, including NAS, Tablet, Game
     console and industrial form factors.

   - Three evaluation boards for TI K3 based SoCs

  The other changes are mainly the usual feature additions for existing
  hardware, cleanups, and dtc compile time fixes. One notable change is
  the inclusion of PowerVR SGX GPU nodes on TI SoCs"

* tag 'soc-dt-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (824 commits)
  riscv: dts: Move BUILTIN_DTB_SOURCE to common Kconfig
  riscv: dts: starfive: jh7100: fix root clock names
  ARM: dts: samsung: exynos4412: decrease memory to account for unusable region
  arm64: dts: qcom: sm8250-xiaomi-elish: set rotation
  arm64: dts: qcom: sm8650: Fix SPMI channels size
  arm64: dts: qcom: sm8550: Fix SPMI channels size
  arm64: dts: rockchip: Fix name for UART pin header on qnap-ts433
  arm: dts: marvell: clearfog-gtr-l8: align port numbers with enclosure
  arm: dts: marvell: clearfog-gtr-l8: add support for second sfp connector
  dt-bindings: soc: renesas: renesas-soc: Add pattern for gray-hawk
  dtc: Enable dtc interrupt_provider check
  arm64: dts: st: add video encoder support to stm32mp255
  arm64: dts: st: add video decoder support to stm32mp255
  ARM: dts: stm32: enable crypto accelerator on stm32mp135f-dk
  ARM: dts: stm32: enable CRC on stm32mp135f-dk
  ARM: dts: stm32: add CRC on stm32mp131
  ARM: dts: add stm32f769-disco-mb1166-reva09
  ARM: dts: stm32: add display support on stm32f769-disco
  ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f769-disco
  ARM: dts: stm32: add DSI support on stm32f769
  ...

1 files changed, 98 insertions, 9 deletions

diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
index c8640cac3edc..00a240484c25 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
@@ -19,6 +19,30 @@
 		stdout-path = &uart1;
 	};
 
+	backlight_lvds: backlight {
+		compatible = "pwm-backlight";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_lvds1>;
+		brightness-levels = <0 4 8 16 32 64 128 255>;
+		default-brightness-level = <11>;
+		enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
+		num-interpolated-steps = <2>;
+		power-supply = <&reg_lvds1_reg_en>;
+		pwms = <&pwm3 0 50000 0>;
+	};
+
+	panel1_lvds: panel-lvds {
+		compatible = "edt,etml1010g3dra";
+		backlight = <&backlight_lvds>;
+		power-supply = <&reg_vcc_3v3_sw>;
+
+		port {
+			panel1_in: endpoint {
+				remote-endpoint = <&ldb_lvds_ch1>;
+			};
+		};
+	};
+
 	reg_can1_stby: regulator-can1-stby {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -39,6 +63,15 @@
 		regulator-name = "can2-stby";
 	};
 
+	reg_lvds1_reg_en: regulator-lvds1 {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		regulator-max-microvolt = <1200000>;
+		regulator-min-microvolt = <1200000>;
+		regulator-name = "lvds1_reg_en";
+	};
+
 	reg_usb1_vbus: regulator-usb1-vbus {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";
@@ -61,6 +94,13 @@
 		startup-delay-us = <100>;
 		off-on-delay-us = <12000>;
 	};
+
+	reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC_3V3_SW";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
 };
 
 &eqos {
@@ -135,10 +175,41 @@
 	};
 };
 
+&lcdif2 {
+	status = "okay";
+};
+
+&lvds_bridge {
+	status = "okay";
+
+	ports {
+		port@2 {
+			ldb_lvds_ch1: endpoint {
+				remote-endpoint = <&panel1_in>;
+			};
+		};
+	};
+};
+
 &snvs_pwrkey {
 	status = "okay";
 };
 
+&pwm3 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pwm3>;
+};
+
+&rv3028 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_rtc>;
+	interrupt-parent = <&gpio4>;
+	interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
+	wakeup-source;
+	trickle-resistor-ohms = <3000>;
+};
+
 /* debug console */
 &uart1 {
 	pinctrl-names = "default";
@@ -239,12 +310,12 @@
 			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90
 			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90
 			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90
-			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16
-			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16
-			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16
-			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16
-			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16
-			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16
+			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x12
+			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x12
+			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x12
+			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x12
+			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x12
+			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x12
 			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20			0x10
 		>;
 	};
@@ -289,16 +360,34 @@
 		>;
 	};
 
+	pinctrl_lvds1: lvds1grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SD2_WP__GPIO2_IO20		0x12
+		>;
+	};
+
+	pinctrl_pwm3: pwm3grp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT		0x12
+		>;
+	};
+
 	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
 		fsl,pins = <
 			MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19	0x40
 		>;
 	};
 
+	pinctrl_rtc: rtcgrp {
+		fsl,pins = <
+			MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19	0x1C0
+		>;
+	};
+
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
-			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x40
-			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x40
+			MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX	0x140
+			MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX	0x140
 		>;
 	};
 
@@ -319,7 +408,7 @@
 
 	pinctrl_usdhc2_pins: usdhc2-gpiogrp {
 		fsl,pins = <
-			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x1c4
+			MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12	0x40
 		>;
 	};