Merge tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu into next/dt

Pull "mvebu dt64 for 4.15 (part 1)" from Gregory CLEMENT:

On Armada 7K/8k:
- Improve network support at SoC and board level
- Enable watchdog
- Add UART muxing
- On 7040 DB: add CD SDIO and NAND support
- On 8040 DB: add PCIE more ports and SPI1

On Armada 37xx:
 - Fix UART register size
 - Add vmmc regulator for SD on 3720 DB

* tag 'mvebu-dt64-4.15-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: 7040-db: Add the carrier detect pin for SD card on CP
  arm64: dts: marvell: 7040-db: Document the gpio expander
  arm64: dts: marvell: enable additional PCIe ports on Armada 8040 DB
  arm64: dts: marvell: add NAND support on the 7040-DB board
  arm64: dts: marvell: Enable Armada-8040-DB CPS SPI1
  arm64: dts: marvell: 8040-db: enable the SFP ports
  arm64: dts: marvell: 7040-db: enable the SFP port
  arm64: dts: marvell: 7040-db: add comphy reference to Ethernet port
  arm64: dts: marvell: mcbin: add comphy references to Ethernet ports
  arm64: dts: marvell: 37xx: remove empty line
  arm64: dts: marvell: cp110: add PPv2 port interrupts
  arm64: dts: marvell: add comphy nodes on cp110 master and slave
  arm64: dts: marvell: extend the cp110 syscon register area length
  arm64: dts: marvell: enable AP806 watchdog
  arm64: dts: marvell: Fix A37xx UART0 register size
  arm64: dts: marvell: armada-3720-db: Add vmmc regulator for SD slot
  arm64: dts: marvell: add UART muxing on Armada 7K/8K

1 files changed, 11 insertions, 0 deletions

diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index 4fbb13d41451..b3350827ee55 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -101,6 +101,8 @@
 
 &uart0 {
 	status = "okay";
+	pinctrl-0 = <&uart0_pins>;
+	pinctrl-names = "default";
 };
 
 &ap_sdhci0 {
@@ -222,8 +224,11 @@
 
 &cpm_eth0 {
 	status = "okay";
+	/* Network PHY */
 	phy = <&phy0>;
 	phy-mode = "10gbase-kr";
+	/* Generic PHY, providing serdes lanes */
+	phys = <&cpm_comphy4 0>;
 };
 
 &cpm_sata0 {
@@ -257,15 +262,21 @@
 
 &cps_eth0 {
 	status = "okay";
+	/* Network PHY */
 	phy = <&phy8>;
 	phy-mode = "10gbase-kr";
+	/* Generic PHY, providing serdes lanes */
+	phys = <&cps_comphy4 0>;
 };
 
 &cps_eth1 {
 	/* CPS Lane 0 - J5 (Gigabit RJ45) */
 	status = "okay";
+	/* Network PHY */
 	phy = <&ge_phy>;
 	phy-mode = "sgmii";
+	/* Generic PHY, providing serdes lanes */
+	phys = <&cps_comphy0 1>;
 };
 
 &cps_pinctrl {