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authorMiquel Raynal <miquel.raynal@bootlin.com>2018-02-19 23:20:44 +0100
committerGregory CLEMENT <gregory.clement@bootlin.com>2018-02-27 17:50:01 +0100
commit1e09a73f321ca67d0d8cfdc5cd156367bc6e0604 (patch)
tree70cd2cfcc74b3f84a390761c2d09dccbf2b20ce9 /arch/arm64/boot/dts/marvell/armada-cp110.dtsi
parentc137ba9b41c739ae7992921182ba94b0b7d52e82 (diff)
arm64: dts: marvell: use reworked NAND controller driver on Armada 7K
Use the new bindings of the reworked Marvell NAND controller driver. Also adapt the nand controller node organization to distinguish which property is relevant for the controller, and which one is NAND chip specific. Expose the partitions as a subnode of the NAND chip. Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as the driver activates the arbiter by default for all boards (either needed or harmless). Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm64/boot/dts/marvell/armada-cp110.dtsi')
-rw-r--r--arch/arm64/boot/dts/marvell/armada-cp110.dtsi8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 215cdc65447c..d3f422f8f086 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -337,17 +337,17 @@
status = "disabled";
};
- CP110_LABEL(nand): nand@720000 {
+ CP110_LABEL(nand_controller): nand@720000 {
/*
* Due to the limitation of the pins available
* this controller is only usable on the CPM
* for A7K and on the CPS for A8K.
*/
- compatible = "marvell,armada-8k-nand",
- "marvell,armada370-nand";
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
#address-cells = <1>;
- #size-cells = <1>;
+ #size-cells = <0>;
interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&CP110_LABEL(clk) 1 2>;
marvell,system-controller = <&CP110_LABEL(syscon0)>;