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authorweiyi.lu@mediatek.com <weiyi.lu@mediatek.com>2018-03-12 15:03:41 +0800
committerMatthias Brugger <matthias.bgg@gmail.com>2018-04-17 16:17:59 +0200
commitf9ce040deb4f4e6b81bea9e61c43ab1b2a961f8a (patch)
tree604dd058bf1c052b0c8adbda4b2939c68d64c036 /arch/arm64/boot/dts/mediatek/mt2712e.dtsi
parent60cc43fc888428bb2f18f08997432d426a243338 (diff)
arm64: dts: add clock device nodes of MT2712
add new clocks according to ECO design change Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'arch/arm64/boot/dts/mediatek/mt2712e.dtsi')
-rw-r--r--arch/arm64/boot/dts/mediatek/mt2712e.dtsi28
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
index 9d88f41aefa0..23f22249ecc1 100644
--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
@@ -199,6 +199,34 @@
clock-output-names = "clkaud_ext_i_2";
};
+ clki2si0_mck_i: oscillator@6 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clki2si0_mck_i";
+ };
+
+ clki2si1_mck_i: oscillator@7 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clki2si1_mck_i";
+ };
+
+ clki2si2_mck_i: oscillator@8 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clki2si2_mck_i";
+ };
+
+ clktdmin_mclk_i: oscillator@9 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <30000000>;
+ clock-output-names = "clktdmin_mclk_i";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;