diff options
| author | Thierry Reding <treding@nvidia.com> | 2020-06-12 09:18:31 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-07-15 11:05:45 +0200 |
| commit | abc9c8a55e7908ff0cd75caa83206d2eac691f20 (patch) | |
| tree | 441c04c40df05857e522d4c03481c98a7fb8577b /arch/arm64/boot/dts/nvidia/tegra132.dtsi | |
| parent | ef126bc4f3d450b236bb82742a5e135d18b0b28b (diff) | |
arm64: tegra: Use sor0_out clock on Tegra132
The sor0_out clock is required to make eDP work properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra132.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra132.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index bac8dd2a09b6..f33b2041c9f4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -141,10 +141,11 @@ reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_SOR0_OUT>, <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, <&tegra_car TEGRA124_CLK_PLL_DP>, <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "out", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; status = "disabled"; |