diff options
author | Sheetal <sheetal@nvidia.com> | 2023-06-29 10:42:16 +0530 |
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committer | Thierry Reding <treding@nvidia.com> | 2023-07-13 17:13:24 +0200 |
commit | e483fe34adab3197558b7284044c1b26f5ede20e (patch) | |
tree | 53ed6fb262d062da3c7fcdfa20c48130e8c496ac /arch/arm64/boot/dts/nvidia/tegra186.dtsi | |
parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) |
arm64: tegra: Update AHUB clock parent and rate on Tegra234
I2S data sanity tests fail beyond a bit clock frequency of 6.144MHz.
This happens because the AHUB clock rate is too low and it shows
9.83MHz on boot.
The maximum rate of PLLA_OUT0 is 49.152MHz and is used to serve I/O
clocks. It is recommended that AHUB clock operates higher than this.
Thus fix this by using PLLP_OUT0 as parent clock for AHUB instead of
PLLA_OUT0 and fix the rate to 81.6MHz.
Fixes: dc94a94daa39 ("arm64: tegra: Add audio devices on Tegra234")
Cc: stable@vger.kernel.org
Signed-off-by: Sheetal <sheetal@nvidia.com>
Signed-off-by: Sameer Pujar <spujar@nvidia.com>
Reviewed-by: Mohan Kumar D <mkumard@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia/tegra186.dtsi')
0 files changed, 0 insertions, 0 deletions