diff options
| author | Thierry Reding <treding@nvidia.com> | 2017-06-26 17:37:09 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-12-13 13:15:42 +0100 |
| commit | 94e25dc3a2b55eb9732f6da41bd25b9dccd60b5a (patch) | |
| tree | 4555b6e7dfff6afacc25d3ddbc53c2c3f5d3ac44 /arch/arm64/boot/dts/nvidia | |
| parent | 029ab5eaf091ce5eaa1f3017f66fd1d10f431d61 (diff) | |
arm64: tegra: Add MISC registers on Tegra186
The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'arch/arm64/boot/dts/nvidia')
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra186.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 46d1f287fb0f..11795dbd30f0 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -13,6 +13,12 @@ #address-cells = <2>; #size-cells = <2>; + misc@100000 { + compatible = "nvidia,tegra186-misc"; + reg = <0x0 0x00100000 0x0 0xf000>, + <0x0 0x0010f000 0x0 0x1000>; + }; + gpio: gpio@2200000 { compatible = "nvidia,tegra186-gpio"; reg-names = "security", "gpio"; |