diff options
| author | Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> | 2019-12-11 04:30:46 +0000 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2019-12-10 22:51:23 -0800 |
| commit | c831fa29999616c500490fd7b4acab2be7fde573 (patch) | |
| tree | d99b95c967deee8695e5c8710c877290a200dd4d /arch/arm64/boot/dts/qcom/sc7180.dtsi | |
| parent | fb2d815006a9aa9df818cb6fa2001d349f4d8d54 (diff) | |
arm64: dts: qcom: sc7180: Add Last level cache controller node
Add device tree node for LLCC aka system cache controller for
SC7180 SoC.
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/0101016ef3394291-2290a8be-91c9-4d46-b5ca-acd5277eb6e2-000000@us-west-2.amazonses.com
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc7180.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc7180.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index a6773ad3738b..e1567109adc4 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -911,6 +911,13 @@ status = "disabled"; }; + system-cache-controller@9200000 { + compatible = "qcom,sc7180-llcc"; + reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; + spmi_bus: spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0 0x0c440000 0 0x1100>, |