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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2023-05-04 19:04:30 +0300
committerBjorn Andersson <andersson@kernel.org>2023-05-24 19:30:43 -0700
commit8721e18ca6960f3c5a6a7f58245d9ab084ad09dd (patch)
tree1f9fa10121b8bd74b0fb7d5052ae83d4643c87ad /arch/arm64/boot/dts/qcom/sdm845-db845c.dts
parent50931b44dc751784cdc5721bf30a79093c2c9fe9 (diff)
arm64: dts: qcom: enable dual ("bonded") DSI mode for DB845c
Now as both lt9611 and drm/msm drivers were updated to handle the 4k modes over DSI, enable "bonded" DSI mode on DB845c. This way the board utilizes both DSI links and thus can support 4k on the HDMI output. Cc: Amit Pundir <amit.pundir@linaro.org> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230504160430.4014206-1-dmitry.baryshkov@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sdm845-db845c.dts')
-rw-r--r--arch/arm64/boot/dts/qcom/sdm845-db845c.dts36
1 files changed, 36 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
index e14fe9bbb386..4dea2c04b22f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
+++ b/arch/arm64/boot/dts/qcom/sdm845-db845c.dts
@@ -419,6 +419,9 @@
status = "okay";
vdda-supply = <&vreg_l26a_1p2>;
+ qcom,dual-dsi-mode;
+ qcom,master-dsi;
+
ports {
port@1 {
endpoint {
@@ -434,6 +437,31 @@
vdds-supply = <&vreg_l1a_0p875>;
};
+&dsi1 {
+ vdda-supply = <&vreg_l26a_1p2>;
+
+ qcom,dual-dsi-mode;
+
+ /* DSI1 is slave, so use DSI0 clocks */
+ assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+ status = "okay";
+
+ ports {
+ port@1 {
+ endpoint {
+ remote-endpoint = <&lt9611_b>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
+&dsi1_phy {
+ vdds-supply = <&vreg_l1a_0p875>;
+ status = "okay";
+};
+
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
@@ -493,6 +521,14 @@
};
};
+ port@1 {
+ reg = <1>;
+
+ lt9611_b: endpoint {
+ remote-endpoint = <&dsi1_out>;
+ };
+ };
+
port@2 {
reg = <2>;