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authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>2021-04-03 02:39:44 +0300
committerBjorn Andersson <bjorn.andersson@linaro.org>2021-04-04 12:38:21 -0500
commit644e4d972d148628b6094258af913b6b38f4da81 (patch)
treec9155bdddb06f208bc73c53cff321002e9f0a667 /arch/arm64/boot/dts/qcom
parent20f9d94e680fb976eb0d7ed253bf791ef3bfc4c9 (diff)
arm64: dts: qcom: sdm845: add required clocks on the gcc
Specify input clocks to the SDM845's Global Clock Controller as required by the bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20210402233944.273275-4-dmitry.baryshkov@linaro.org Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts/qcom')
-rw-r--r--arch/arm64/boot/dts/qcom/sdm845.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 7395ef20b90e..0b2077bce8fa 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1061,6 +1061,16 @@
gcc: clock-controller@100000 {
compatible = "qcom,gcc-sdm845";
reg = <0 0x00100000 0 0x1f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>,
+ <&pcie0_lane>,
+ <&pcie1_lane>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk",
+ "pcie_0_pipe_clk",
+ "pcie_1_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
@@ -2062,6 +2072,7 @@
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_0_pipe_clk";
};
@@ -2170,6 +2181,7 @@
clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
clock-names = "pipe0";
+ #clock-cells = <0>;
#phy-cells = <0>;
clock-output-names = "pcie_1_pipe_clk";
};