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authorBiju Das <biju.das.jz@bp.renesas.com>2022-02-03 17:06:35 +0000
committerGeert Uytterhoeven <geert+renesas@glider.be>2022-02-08 09:45:59 +0100
commitfa00d6dc19283bee13f0390546f741293f6d2d9a (patch)
tree1408bd53ae1cecd295f9a42debd64c4ac4659713 /arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
parent2ed3b5d9540b246d7a1ec98971914ee810b40086 (diff)
arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
SCIF1 interface is available on PMOD1 connector (CN7) on carrier board. This patch adds pinmux and scif1 node to carrier board dtsi file for RZ/G2LC SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Link: https://lore.kernel.org/r/20220203170636.7747-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi')
-rw-r--r--arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
index 1032f6563515..ec9e08ec0822 100644
--- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
@@ -17,6 +17,13 @@
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
};
+ scif1_pins: scif1 {
+ pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
+ <RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
+ <RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
+ <RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
+ };
+
sd1-pwr-en-hog {
gpio-hog;
gpios = <RZG2L_GPIO(39, 2) GPIO_ACTIVE_HIGH>;