Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM Devicetree updates from Olof Johansson:
 "As usual, most of the changes are to devicetrees.

  Besides smaller fixes, some refactorings and cleanups, some of the new
  platforms and chips (or significant features) supported are below:

  Broadcom boards:
   - Cisco Meraki MR32 (BCM53016-based)
   - BCM2711 (RPi4) display pipeline support

  Actions Semi boards:
   - Caninos Loucos Labrador SBC (S500-based)
   - RoseapplePi SBC (S500-based)

  Allwinner SoCs/boards:
   - A100 SoC with Perf1 board
   - Mali, DMA, Cetrus and IR support for R40 SoC

  Amlogic boards:
   - Libretch S905x CC V2 board
   - Hardkernel ODROID-N2+ board

  Aspeed boards/platforms:
   - Wistron Mowgli (AST2500-based, Power9 OpenPower server)
   - Facebook Wedge400 (AST2500-based, ToR switch)

  Hisilicon SoC:
   - SD5203 SoC

  Nvidia boards:
   - Tegra234 VDK, for pre-silicon Orin SoC

  NXP i.MX boards:
   - Librem 5 phone
   - i.MX8MM DDR4 EVK
   - Variscite VAR-SOM-MX8MN SoM
   - Symphony board
   - Tolino Shine 2 HD
   - TQMa6 SoM
   - Y Soft IOTA Orion

  Rockchip boards:
   - NanoPi R2S board
   - A95X-Z2 board
   - more Rock-Pi4 variants

  STM32 boards:
   - Odyssey SOM board (STM32MP157CAC-based)
   - DH DRC02 board

  Toshiba SoCs/boards:
   - Visconti SoC and TPMV7708 board"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (638 commits)
  ARM: dts: nspire: Fix SP804 users
  arm64: dts: lg: Fix SP804 users
  arm64: dts: lg: Fix SP805 clocks
  ARM: mstar: Fix up the fallout from moving the dts/dtsi files
  ARM: mstar: Add mstar prefix to all of the dtsi/dts files
  ARM: mstar: Add interrupt to pm_uart
  ARM: mstar: Add interrupt controller to base dtsi
  ARM: dts: meson8: remove two invalid interrupt lines from the GPU node
  arm64: dts: ti: k3-j7200-common-proc-board: Add USB support
  arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
  arm64: dts: ti: k3-j7200-main: Add USB controller
  arm64: dts: ti: k3-j7200-main.dtsi: Add USB to SERDES lane MUX
  arm64: dts: ti: k3-j7200-main: Add SERDES lane control mux
  dt-bindings: ti-serdes-mux: Add defines for J7200 SoC
  ARM: dts: hisilicon: add SD5203 dts
  ARM: dts: hisilicon: fix the system controller compatible nodes
  arm64: dts: zynqmp: Fix leds subnode name for zcu100/ultra96 v1
  arm64: dts: zynqmp: Remove undocumented u-boot properties
  arm64: dts: zynqmp: Remove additional compatible string for i2c IPs
  arm64: dts: zynqmp: Rename buses to be align with simple-bus yaml
  ...

1 files changed, 7 insertions, 4 deletions

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index d035b61e0e16..cc483f7344af 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -120,21 +120,24 @@
 		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
-	cbass_main: interconnect@100000 {
+	cbass_main: bus@100000 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
 			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
 			 <0x00 0x00900000 0x00 0x00900000 0x00 0x00012000>, /* serdes */
-			 <0x00 0x00A40000 0x00 0x00A40000 0x00 0x00000800>, /* timesync router */
+			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* timesync router */
 			 <0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
 			 <0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
 			 <0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
 			 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
-			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
+			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
+			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
 			 <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
 			 <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
+			 <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
+			 <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
 			 <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
 			 <0x4d 0x81800000 0x4d 0x81800000 0x00 0x00800000>, /* C66_1 */
 			 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
@@ -155,7 +158,7 @@
 			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
 			 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
 
-		cbass_mcu_wakeup: interconnect@28380000 {
+		cbass_mcu_wakeup: bus@28380000 {
 			compatible = "simple-bus";
 			#address-cells = <2>;
 			#size-cells = <2>;