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authorStephan Gerhold <stephan@gerhold.net>2020-04-26 16:06:39 +0200
committerBjorn Andersson <bjorn.andersson@linaro.org>2020-05-12 11:22:08 -0700
commit428384b535d65a8b3c5164c7600d7db5223c4707 (patch)
tree997b921a4afd294d217841ecaa5cc2c87759a574 /arch/arm64/boot/dts
parent0f1decaa83b7fc7a2a1effb6d53eac39a037f06b (diff)
arm64: dts: qcom: msm8916: Add blsp_i2c1
MSM8916 has another I2C QUP controller that can be enabled on GPIO 2 and 3. Add blsp_i2c1 to msm8916.dtsi and disable it by default. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Link: https://lore.kernel.org/r/20200426140642.204395-2-stephan@gerhold.net Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts')
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916-pins.dtsi24
-rw-r--r--arch/arm64/boot/dts/qcom/msm8916.dtsi15
2 files changed, 39 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 242aaea68804..b45fd12856ea 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -262,6 +262,30 @@
};
};
+ i2c1_default: i2c1_default {
+ pinmux {
+ function = "blsp_i2c1";
+ pins = "gpio2", "gpio3";
+ };
+ pinconf {
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
+ i2c1_sleep: i2c1_sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio2", "gpio3";
+ };
+ pinconf {
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+
i2c2_default: i2c2_default {
pinmux {
function = "blsp_i2c2";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 8b429954ea29..6ab7cabde370 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -612,6 +612,21 @@
status = "disabled";
};
+ blsp_i2c1: i2c@78b5000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b5000 0x500>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-1 = <&i2c1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>;