diff options
| author | Bhupesh Sharma <bhupesh.sharma@linaro.org> | 2021-07-06 19:08:14 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2021-07-20 08:58:12 -0500 |
| commit | 98aee1e3cdcd74debc093cfc9297287063e88a0f (patch) | |
| tree | f1d8a32e5024428a2267074dfd711fed6b9f743e /arch/arm64/boot/dts | |
| parent | 63fa4322469648ae1023bb92a8b0d6a2f4bdaf2c (diff) | |
arm64: dts: qcom: sm8150: Add UFS ICE capability
Add support for UFS ICE (Qualcomm Inline Crypto Engine) in
sm8150 SoC dts.
I tested this on SA8155p-adp board, which is a publicly
available development board that uses the sa8155p Qualcomm
Snapdragon SoC. SA8155p platform is similar to the SM8150,
so use this as base for now.
I tested the UFS ICE feature using 'fscrypt' test utility.
Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Eric Biggers <ebiggers@google.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20210706133814.621536-1-bhupesh.sharma@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Diffstat (limited to 'arch/arm64/boot/dts')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8150.dtsi | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 965670489830..1c84d78d0a19 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1331,7 +1331,9 @@ ufs_mem_hc: ufshc@1d84000 { compatible = "qcom,sm8150-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg = <0 0x01d84000 0 0x2500>; + reg = <0 0x01d84000 0 0x2500>, + <0 0x01d90000 0 0x8000>; + reg-names = "std", "ice"; interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; phys = <&ufs_mem_phy_lanes>; phy-names = "ufsphy"; @@ -1350,7 +1352,8 @@ "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", - "rx_lane1_sync_clk"; + "rx_lane1_sync_clk", + "ice_core_clk"; clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, @@ -1359,7 +1362,8 @@ <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, - <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; freq-table-hz = <37500000 300000000>, <0 0>, @@ -1368,7 +1372,8 @@ <0 0>, <0 0>, <0 0>, - <0 0>; + <0 0>, + <0 300000000>; status = "disabled"; }; |