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| author | Arnd Bergmann <arnd@arndb.de> | 2019-09-03 15:10:33 +0200 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2019-09-03 15:10:33 +0200 |
| commit | aa85a28663a8477ba2608c6a9cc08539c1dd6603 (patch) | |
| tree | 2e9221a37c1a2b3cb96a78aa7ec5b674a7d86fce /arch/arm64/boot | |
| parent | 2c70bcf72dc6b42720e6eff5a71ee82fe8ccd2c3 (diff) | |
| parent | d8c1ccac448fd21a3753517a34ee0164c28ac786 (diff) | |
Merge tag 'socfpga_dts_updates_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into arm/dt
SoCFPGA DTS updates for v5.4
- Add reset properties for various peripherals
- QSPI OCP and DMA on Arria10
- DMA on Agilex/Stratix10
- Update NAND controller bindings to match driver update
- Add NAND controller to Stratix10
- VINING FPGA board fixups
- Update button mapping
- Adjust GMAC1 clock and TXD skew settings
- Add missing reset-names for dma controller
* tag 'socfpga_dts_updates_for_v5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: add missing reset-names for dma
ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA
ARM: dts: socfpga: Fix up button mapping on VINING FPGA
arm64: dts: stratix10: Add NAND device node
ARM: dts: socfpga: update to new Denali NAND binding
arm64: dts: agilex/stratix10: Add reset properties for DMA
ARM: dts: socfpga: add reset properties for DMA
ARM: dts: socfpga: add the QSPI OCP reset property on arria10
Link: https://lore.kernel.org/r/20190819141659.26414-1-dinguyen@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm64/boot')
| -rw-r--r-- | arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 18 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 |
2 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index b05d78164fc1..144a2c19ac02 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -302,6 +302,22 @@ status = "disabled"; }; + nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + clocks = <&clkmgr STRATIX10_NAND_CLK>, + <&clkmgr STRATIX10_NAND_X_CLK>, + <&clkmgr STRATIX10_NAND_ECC_CLK>; + clock-names = "nand", "nand_x", "ecc"; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>; @@ -324,6 +340,8 @@ #dma-requests = <32>; clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; clock-names = "apb_pclk"; + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; + reset-names = "dma", "dma-ocp"; }; rst: rstmgr@ffd11000 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index e4ceb3a73c81..36abc25320a8 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -249,6 +249,8 @@ #dma-cells = <1>; #dma-channels = <8>; #dma-requests = <32>; + resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>; + reset-names = "dma", "dma-ocp"; }; rst: rstmgr@ffd11000 { |