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authorWill Deacon <will.deacon@arm.com>2017-03-10 20:32:21 +0000
committerCatalin Marinas <catalin.marinas@arm.com>2017-03-20 16:16:54 +0000
commita8d4636f96ad075dc6d6af182b3de0b5498dc301 (patch)
treeba0483ccb5c180e1f341b0ca5b7773941b959553 /arch/arm64/include/asm/cache.h
parent3689c75af2a3bc944826e6da663deee50c97d910 (diff)
arm64: cacheinfo: Remove CCSIDR-based cache information probing
The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use in conjunction with set/way cache maintenance and are not guaranteed to represent the actual microarchitectural features of a design. The architecture explicitly states: | You cannot make any inference about the actual sizes of caches based | on these parameters. Furthermore, CCSIDR_EL1.{WT,WB,RA,WA} have been removed retrospectively from ARMv8 and are now considered to be UNKNOWN. Since the kernel doesn't make use of set/way cache maintenance and it is not possible for userspace to execute these instructions, we have no need for the CCSIDR information in the kernel. This patch removes the accessors, along with the related portions of the cacheinfo support, which should instead be reintroduced when firmware has a mechanism to provide us with reliable information. Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cache.h')
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