diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2017-12-03 17:47:03 +0000 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2018-03-19 13:05:10 +0000 |
| commit | 9f2efa320d395050abd0f39842843bb460736515 (patch) | |
| tree | 769cc9c3900c0a8ae5d8f49172bd6d9d06f86ade /arch/arm64/include/asm/insn.h | |
| parent | e3f019b37b580c3b954419212da26ac5db412a08 (diff) | |
arm64; insn: Add encoder for the EXTR instruction
Add an encoder for the EXTR instruction, which also implements the ROR
variant (where Rn == Rm).
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/insn.h')
| -rw-r--r-- | arch/arm64/include/asm/insn.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h index 815b35bc53ed..f62c56b1793f 100644 --- a/arch/arm64/include/asm/insn.h +++ b/arch/arm64/include/asm/insn.h @@ -319,6 +319,7 @@ __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000) __AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000) __AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000) __AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000) +__AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000) __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) __AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000) @@ -433,6 +434,11 @@ u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type, enum aarch64_insn_register Rn, enum aarch64_insn_register Rd, u64 imm); +u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant, + enum aarch64_insn_register Rm, + enum aarch64_insn_register Rn, + enum aarch64_insn_register Rd, + u8 lsb); u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base, enum aarch64_insn_prfm_type type, enum aarch64_insn_prfm_target target, |