diff options
| author | Will Deacon <will.deacon@arm.com> | 2018-12-13 13:47:38 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-13 14:14:21 +0000 |
| commit | 2a355ec25729053bb9a1a89b6c1d1cdd6c3b3fb1 (patch) | |
| tree | eb156e26883d666f26909dfa50d3d206848f885f /arch/arm64/include/asm/perf_event.h | |
| parent | b47f515bdcd4e22b0b87141157c9ee8bc7c9bb98 (diff) | |
arm64: kpti: Whitelist Cortex-A CPUs that don't implement the CSV3 field
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.
We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/perf_event.h')
0 files changed, 0 insertions, 0 deletions