diff options
| author | Marc Zyngier <marc.zyngier@arm.com> | 2019-05-23 11:24:50 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2019-05-23 15:40:30 +0100 |
| commit | a5325089bd05a7b0259cc4038479d36308edbda2 (patch) | |
| tree | 253c14c201d292126e4166f88b397642cdedd90c /arch/arm64/kernel/entry.S | |
| parent | 1cf24a2cc3fd40942b0f9e6199aaec579e89a832 (diff) | |
arm64: Handle erratum 1418040 as a superset of erratum 1188873
We already mitigate erratum 1188873 affecting Cortex-A76 and
Neoverse-N1 r0p0 to r2p0. It turns out that revisions r0p0 to
r3p1 of the same cores are affected by erratum 1418040, which
has the same workaround as 1188873.
Let's expand the range of affected revisions to match 1418040,
and repaint all occurences of 1188873 to 1418040. Whilst we're
there, do a bit of reformating in silicon-errata.txt and drop
a now unnecessary dependency on ARM_ARCH_TIMER_OOL_WORKAROUND.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'arch/arm64/kernel/entry.S')
| -rw-r--r-- | arch/arm64/kernel/entry.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index 1a7811b7e3c4..cd0c7af8e4a8 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -336,8 +336,8 @@ alternative_if ARM64_WORKAROUND_845719 alternative_else_nop_endif #endif 3: -#ifdef CONFIG_ARM64_ERRATUM_1188873 -alternative_if_not ARM64_WORKAROUND_1188873 +#ifdef CONFIG_ARM64_ERRATUM_1418040 +alternative_if_not ARM64_WORKAROUND_1418040 b 4f alternative_else_nop_endif /* |