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| author | Catalin Marinas <catalin.marinas@arm.com> | 2023-06-23 18:34:16 +0100 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2023-06-23 18:34:16 +0100 |
| commit | abc17128c81ae8d6a091f24348c63cbe8fe59724 (patch) | |
| tree | 90dc9c2268fc399b0aa812cab6e223859720a741 /arch/arm64/mm/fault.c | |
| parent | f42039d10b0f1d0075568df1d64df31f5cc90e92 (diff) | |
| parent | 5f0419a0083b304566fa32c27a0f009634a7f703 (diff) | |
Merge branch 'for-next/feat_s1pie' into for-next/core
* for-next/feat_s1pie:
: Support for the Armv8.9 Permission Indirection Extensions (stage 1 only)
KVM: selftests: get-reg-list: add Permission Indirection registers
KVM: selftests: get-reg-list: support ID register features
arm64: Document boot requirements for PIE
arm64: transfer permission indirection settings to EL2
arm64: enable Permission Indirection Extension (PIE)
arm64: add encodings of PIRx_ELx registers
arm64: disable EL2 traps for PIE
arm64: reorganise PAGE_/PROT_ macros
arm64: add PTE_WRITE to PROT_SECT_NORMAL
arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
KVM: arm64: expose ID_AA64MMFR3_EL1 to guests
KVM: arm64: Save/restore PIE registers
KVM: arm64: Save/restore TCR2_EL1
arm64: cpufeature: add Permission Indirection Extension cpucap
arm64: cpufeature: add TCR2 cpucap
arm64: cpufeature: add system register ID_AA64MMFR3
arm64/sysreg: add PIR*_ELx registers
arm64/sysreg: update HCRX_EL2 register
arm64/sysreg: add system registers TCR2_ELx
arm64/sysreg: Add ID register ID_AA64MMFR3
Diffstat (limited to 'arch/arm64/mm/fault.c')
0 files changed, 0 insertions, 0 deletions