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| author | Catalin Marinas <catalin.marinas@arm.com> | 2025-03-25 19:32:32 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2025-03-25 19:32:32 +0000 |
| commit | 64fa6b9322a904198589c0479dca6f2ed7f2eb04 (patch) | |
| tree | 32fd467440b4748fc0762b33faa1fcb3ca57a4ed /arch/arm64 | |
| parent | 8ae9e2d8325698edc1335ede5401f68bcd7cc400 (diff) | |
| parent | 858c7bfcb35e1100b58bb63c9f562d86e09418d9 (diff) | |
Merge branch 'for-next/el2-enable-feat-pmuv3p9' into for-next/core
* for-next/el2-enable-feat-pmuv3p9:
: Enable EL2 requirements for FEAT_PMUv3p9
arm64/boot: Enable EL2 requirements for FEAT_PMUv3p9
Diffstat (limited to 'arch/arm64')
| -rw-r--r-- | arch/arm64/include/asm/el2_setup.h | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h index 25e162651750..1a0071faf57e 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -233,6 +233,30 @@ .Lskip_fgt_\@: .endm +.macro __init_el2_fgt2 + mrs x1, id_aa64mmfr0_el1 + ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 + cmp x1, #ID_AA64MMFR0_EL1_FGT_FGT2 + b.lt .Lskip_fgt2_\@ + + mov x0, xzr + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 + cmp x1, #ID_AA64DFR0_EL1_PMUVer_V3P9 + b.lt .Lskip_pmuv3p9_\@ + + orr x0, x0, #HDFGRTR2_EL2_nPMICNTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 + orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 +.Lskip_pmuv3p9_\@: + msr_s SYS_HDFGRTR2_EL2, x0 + msr_s SYS_HDFGWTR2_EL2, x0 + msr_s SYS_HFGRTR2_EL2, xzr + msr_s SYS_HFGWTR2_EL2, xzr + msr_s SYS_HFGITR2_EL2, xzr +.Lskip_fgt2_\@: +.endm + .macro __init_el2_gcs mrs_s x1, SYS_ID_AA64PFR1_EL1 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 @@ -283,6 +307,7 @@ __init_el2_nvhe_idregs __init_el2_cptr __init_el2_fgt + __init_el2_fgt2 __init_el2_gcs .endm |