CRIS: Drop support for the CRIS port

The port was added back in 2000 so it's no longer even a good source
of inspiration for newer ports (if it ever was)

The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008.

Coupled with time and working developer board hardware being
in low supply, it's time to drop the port from Linux.

So long and thanks for all the fish!

Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

21 files changed, 0 insertions, 8936 deletions

diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h
deleted file mode 100644
index 10443d789a66..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_crc_par_defs_asm.h
+++ /dev/null
@@ -1,172 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_crc_par_defs_asm_h
-#define __iop_crc_par_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_crc_par.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_crc_par_defs_asm.h ../../inst/io_proc/rtl/iop_crc_par.r
- *      id: $Id: iop_crc_par_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_cfg___mode___lsb 0
-#define reg_iop_crc_par_rw_cfg___mode___width 1
-#define reg_iop_crc_par_rw_cfg___mode___bit 0
-#define reg_iop_crc_par_rw_cfg___crc_out___lsb 1
-#define reg_iop_crc_par_rw_cfg___crc_out___width 1
-#define reg_iop_crc_par_rw_cfg___crc_out___bit 1
-#define reg_iop_crc_par_rw_cfg___rev_out___lsb 2
-#define reg_iop_crc_par_rw_cfg___rev_out___width 1
-#define reg_iop_crc_par_rw_cfg___rev_out___bit 2
-#define reg_iop_crc_par_rw_cfg___inv_out___lsb 3
-#define reg_iop_crc_par_rw_cfg___inv_out___width 1
-#define reg_iop_crc_par_rw_cfg___inv_out___bit 3
-#define reg_iop_crc_par_rw_cfg___trig___lsb 4
-#define reg_iop_crc_par_rw_cfg___trig___width 2
-#define reg_iop_crc_par_rw_cfg___poly___lsb 6
-#define reg_iop_crc_par_rw_cfg___poly___width 3
-#define reg_iop_crc_par_rw_cfg_offset 0
-
-/* Register rw_init_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_init_crc_offset 4
-
-/* Register rw_correct_crc, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_correct_crc_offset 8
-
-/* Register rw_ctrl, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_ctrl___en___lsb 0
-#define reg_iop_crc_par_rw_ctrl___en___width 1
-#define reg_iop_crc_par_rw_ctrl___en___bit 0
-#define reg_iop_crc_par_rw_ctrl_offset 12
-
-/* Register rw_set_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_set_last___tr_dif___lsb 0
-#define reg_iop_crc_par_rw_set_last___tr_dif___width 1
-#define reg_iop_crc_par_rw_set_last___tr_dif___bit 0
-#define reg_iop_crc_par_rw_set_last_offset 16
-
-/* Register rw_wr1byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_offset 20
-
-/* Register rw_wr2byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_offset 24
-
-/* Register rw_wr3byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_offset 28
-
-/* Register rw_wr4byte, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_offset 32
-
-/* Register rw_wr1byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr1byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr1byte_last___data___width 8
-#define reg_iop_crc_par_rw_wr1byte_last_offset 36
-
-/* Register rw_wr2byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr2byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr2byte_last___data___width 16
-#define reg_iop_crc_par_rw_wr2byte_last_offset 40
-
-/* Register rw_wr3byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr3byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr3byte_last___data___width 24
-#define reg_iop_crc_par_rw_wr3byte_last_offset 44
-
-/* Register rw_wr4byte_last, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_wr4byte_last___data___lsb 0
-#define reg_iop_crc_par_rw_wr4byte_last___data___width 32
-#define reg_iop_crc_par_rw_wr4byte_last_offset 48
-
-/* Register r_stat, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_stat___err___lsb 0
-#define reg_iop_crc_par_r_stat___err___width 1
-#define reg_iop_crc_par_r_stat___err___bit 0
-#define reg_iop_crc_par_r_stat___busy___lsb 1
-#define reg_iop_crc_par_r_stat___busy___width 1
-#define reg_iop_crc_par_r_stat___busy___bit 1
-#define reg_iop_crc_par_r_stat_offset 52
-
-/* Register r_sh_reg, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_sh_reg_offset 56
-
-/* Register r_crc, scope iop_crc_par, type r */
-#define reg_iop_crc_par_r_crc_offset 60
-
-/* Register rw_strb_rec_dif_in, scope iop_crc_par, type rw */
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___lsb 0
-#define reg_iop_crc_par_rw_strb_rec_dif_in___last___width 2
-#define reg_iop_crc_par_rw_strb_rec_dif_in_offset 64
-
-
-/* Constants */
-#define regk_iop_crc_par_calc                     0x00000001
-#define regk_iop_crc_par_ccitt                    0x00000002
-#define regk_iop_crc_par_check                    0x00000000
-#define regk_iop_crc_par_crc16                    0x00000001
-#define regk_iop_crc_par_crc32                    0x00000000
-#define regk_iop_crc_par_crc5                     0x00000003
-#define regk_iop_crc_par_crc5_11                  0x00000004
-#define regk_iop_crc_par_dif_in                   0x00000002
-#define regk_iop_crc_par_hi                       0x00000000
-#define regk_iop_crc_par_neg                      0x00000002
-#define regk_iop_crc_par_no                       0x00000000
-#define regk_iop_crc_par_pos                      0x00000001
-#define regk_iop_crc_par_pos_neg                  0x00000003
-#define regk_iop_crc_par_rw_cfg_default           0x00000000
-#define regk_iop_crc_par_rw_ctrl_default          0x00000000
-#define regk_iop_crc_par_yes                      0x00000001
-#endif /* __iop_crc_par_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h
deleted file mode 100644
index fdee9bbe1fd4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_in_defs_asm.h
+++ /dev/null
@@ -1,322 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_in_defs_asm_h
-#define __iop_dmc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_dmc_in.r
- *     id:           iop_dmc_in.r,v 1.26 2005/02/16 09:14:17 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_in_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_in.r
- *      id: $Id: iop_dmc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_cfg___sth_intr___lsb 0
-#define reg_iop_dmc_in_rw_cfg___sth_intr___width 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___lsb 3
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___width 1
-#define reg_iop_dmc_in_rw_cfg___last_dis_dif___bit 3
-#define reg_iop_dmc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_in_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_in_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___lsb 2
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___width 1
-#define reg_iop_dmc_in_rw_ctrl___stream_clr___bit 2
-#define reg_iop_dmc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_in_r_stat___dif_en___width 1
-#define reg_iop_dmc_in_r_stat___dif_en___bit 0
-#define reg_iop_dmc_in_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_in_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_in_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_in_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_in_rw_stream_cmd_offset 12
-
-/* Register rw_stream_wr_data, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_offset 16
-
-/* Register rw_stream_wr_data_last, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_wr_data_last_offset 20
-
-/* Register rw_stream_ctrl, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___lsb 0
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___eop___bit 0
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___lsb 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___wait___bit 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___lsb 2
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___width 1
-#define reg_iop_dmc_in_rw_stream_ctrl___keep_md___bit 2
-#define reg_iop_dmc_in_rw_stream_ctrl___size___lsb 3
-#define reg_iop_dmc_in_rw_stream_ctrl___size___width 3
-#define reg_iop_dmc_in_rw_stream_ctrl_offset 24
-
-/* Register r_stream_stat, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_stream_stat___sth___lsb 0
-#define reg_iop_dmc_in_r_stream_stat___sth___width 7
-#define reg_iop_dmc_in_r_stream_stat___full___lsb 16
-#define reg_iop_dmc_in_r_stream_stat___full___width 1
-#define reg_iop_dmc_in_r_stream_stat___full___bit 16
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___lsb 17
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___width 1
-#define reg_iop_dmc_in_r_stream_stat___last_pkt___bit 17
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___lsb 18
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___data_md_valid___bit 18
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___lsb 19
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___ctxt_md_valid___bit 19
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___lsb 20
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_in_r_stream_stat___group_md_valid___bit 20
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___lsb 21
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_in_r_stream_stat___stream_busy___bit 21
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___lsb 22
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_stream_stat___cmd_rdy___bit 22
-#define reg_iop_dmc_in_r_stream_stat_offset 28
-
-/* Register r_data_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_data_descr___stat___width 8
-#define reg_iop_dmc_in_r_data_descr___md___lsb 16
-#define reg_iop_dmc_in_r_data_descr___md___width 16
-#define reg_iop_dmc_in_r_data_descr_offset 32
-
-/* Register r_ctxt_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_in_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_r_ctxt_descr_offset 36
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md1_offset 40
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_ctxt_descr_md2_offset 44
-
-/* Register r_group_descr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_in_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_in_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_in_r_group_descr___stat___width 8
-#define reg_iop_dmc_in_r_group_descr___md___lsb 16
-#define reg_iop_dmc_in_r_group_descr___md___width 16
-#define reg_iop_dmc_in_r_group_descr_offset 56
-
-/* Register rw_data_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_data_descr___md___width 16
-#define reg_iop_dmc_in_rw_data_descr_offset 60
-
-/* Register rw_ctxt_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_in_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_in_rw_ctxt_descr_offset 64
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md1_offset 68
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ctxt_descr_md2_offset 72
-
-/* Register rw_group_descr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_in_rw_group_descr___md___width 16
-#define reg_iop_dmc_in_rw_group_descr_offset 84
-
-/* Register rw_intr_mask, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_in_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_in_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_in_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_intr_mask___sth___lsb 4
-#define reg_iop_dmc_in_rw_intr_mask___sth___width 1
-#define reg_iop_dmc_in_rw_intr_mask___sth___bit 4
-#define reg_iop_dmc_in_rw_intr_mask___full___lsb 5
-#define reg_iop_dmc_in_rw_intr_mask___full___width 1
-#define reg_iop_dmc_in_rw_intr_mask___full___bit 5
-#define reg_iop_dmc_in_rw_intr_mask_offset 88
-
-/* Register rw_ack_intr, scope iop_dmc_in, type rw */
-#define reg_iop_dmc_in_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_in_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_in_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_in_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_rw_ack_intr___sth___lsb 4
-#define reg_iop_dmc_in_rw_ack_intr___sth___width 1
-#define reg_iop_dmc_in_rw_ack_intr___sth___bit 4
-#define reg_iop_dmc_in_rw_ack_intr___full___lsb 5
-#define reg_iop_dmc_in_rw_ack_intr___full___width 1
-#define reg_iop_dmc_in_rw_ack_intr___full___bit 5
-#define reg_iop_dmc_in_rw_ack_intr_offset 92
-
-/* Register r_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_intr___data_md___width 1
-#define reg_iop_dmc_in_r_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_intr___group_md___width 1
-#define reg_iop_dmc_in_r_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_intr___sth___width 1
-#define reg_iop_dmc_in_r_intr___sth___bit 4
-#define reg_iop_dmc_in_r_intr___full___lsb 5
-#define reg_iop_dmc_in_r_intr___full___width 1
-#define reg_iop_dmc_in_r_intr___full___bit 5
-#define reg_iop_dmc_in_r_intr_offset 96
-
-/* Register r_masked_intr, scope iop_dmc_in, type r */
-#define reg_iop_dmc_in_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_in_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_in_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_in_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_in_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_in_r_masked_intr___sth___lsb 4
-#define reg_iop_dmc_in_r_masked_intr___sth___width 1
-#define reg_iop_dmc_in_r_masked_intr___sth___bit 4
-#define reg_iop_dmc_in_r_masked_intr___full___lsb 5
-#define reg_iop_dmc_in_r_masked_intr___full___width 1
-#define reg_iop_dmc_in_r_masked_intr___full___bit 5
-#define reg_iop_dmc_in_r_masked_intr_offset 100
-
-
-/* Constants */
-#define regk_iop_dmc_in_ack_pkt                   0x00000100
-#define regk_iop_dmc_in_array                     0x00000008
-#define regk_iop_dmc_in_burst                     0x00000020
-#define regk_iop_dmc_in_copy_next                 0x00000010
-#define regk_iop_dmc_in_copy_up                   0x00000020
-#define regk_iop_dmc_in_dis_c                     0x00000010
-#define regk_iop_dmc_in_dis_g                     0x00000020
-#define regk_iop_dmc_in_lim1                      0x00000000
-#define regk_iop_dmc_in_lim16                     0x00000004
-#define regk_iop_dmc_in_lim2                      0x00000001
-#define regk_iop_dmc_in_lim32                     0x00000005
-#define regk_iop_dmc_in_lim4                      0x00000002
-#define regk_iop_dmc_in_lim64                     0x00000006
-#define regk_iop_dmc_in_lim8                      0x00000003
-#define regk_iop_dmc_in_load_c                    0x00000200
-#define regk_iop_dmc_in_load_c_n                  0x00000280
-#define regk_iop_dmc_in_load_c_next               0x00000240
-#define regk_iop_dmc_in_load_d                    0x00000140
-#define regk_iop_dmc_in_load_g                    0x00000300
-#define regk_iop_dmc_in_load_g_down               0x000003c0
-#define regk_iop_dmc_in_load_g_next               0x00000340
-#define regk_iop_dmc_in_load_g_up                 0x00000380
-#define regk_iop_dmc_in_next_en                   0x00000010
-#define regk_iop_dmc_in_next_pkt                  0x00000010
-#define regk_iop_dmc_in_no                        0x00000000
-#define regk_iop_dmc_in_restore                   0x00000020
-#define regk_iop_dmc_in_rw_cfg_default            0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_default     0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md1_default  0x00000000
-#define regk_iop_dmc_in_rw_ctxt_descr_md2_default  0x00000000
-#define regk_iop_dmc_in_rw_data_descr_default     0x00000000
-#define regk_iop_dmc_in_rw_group_descr_default    0x00000000
-#define regk_iop_dmc_in_rw_intr_mask_default      0x00000000
-#define regk_iop_dmc_in_rw_stream_ctrl_default    0x00000000
-#define regk_iop_dmc_in_save_down                 0x00000020
-#define regk_iop_dmc_in_save_up                   0x00000020
-#define regk_iop_dmc_in_set_reg                   0x00000050
-#define regk_iop_dmc_in_set_w_size1               0x00000190
-#define regk_iop_dmc_in_set_w_size2               0x000001a0
-#define regk_iop_dmc_in_set_w_size4               0x000001c0
-#define regk_iop_dmc_in_store_c                   0x00000002
-#define regk_iop_dmc_in_store_descr               0x00000000
-#define regk_iop_dmc_in_store_g                   0x00000004
-#define regk_iop_dmc_in_store_md                  0x00000001
-#define regk_iop_dmc_in_update_down               0x00000020
-#define regk_iop_dmc_in_yes                       0x00000001
-#endif /* __iop_dmc_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h
deleted file mode 100644
index a97b741bd36a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_dmc_out_defs_asm.h
+++ /dev/null
@@ -1,350 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_dmc_out_defs_asm_h
-#define __iop_dmc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_dmc_out.r
- *     id:           iop_dmc_out.r,v 1.30 2005/02/16 09:14:11 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_dmc_out_defs_asm.h ../../inst/io_proc/rtl/iop_dmc_out.r
- *      id: $Id: iop_dmc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_cfg___trf_lim___lsb 0
-#define reg_iop_dmc_out_rw_cfg___trf_lim___width 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___lsb 16
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___width 1
-#define reg_iop_dmc_out_rw_cfg___last_at_trf_lim___bit 16
-#define reg_iop_dmc_out_rw_cfg___dth_intr___lsb 17
-#define reg_iop_dmc_out_rw_cfg___dth_intr___width 3
-#define reg_iop_dmc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctrl___dif_en___lsb 0
-#define reg_iop_dmc_out_rw_ctrl___dif_en___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_en___bit 0
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___lsb 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___width 1
-#define reg_iop_dmc_out_rw_ctrl___dif_dis___bit 1
-#define reg_iop_dmc_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stat___dif_en___lsb 0
-#define reg_iop_dmc_out_r_stat___dif_en___width 1
-#define reg_iop_dmc_out_r_stat___dif_en___bit 0
-#define reg_iop_dmc_out_r_stat_offset 8
-
-/* Register rw_stream_cmd, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___lsb 0
-#define reg_iop_dmc_out_rw_stream_cmd___cmd___width 10
-#define reg_iop_dmc_out_rw_stream_cmd___n___lsb 16
-#define reg_iop_dmc_out_rw_stream_cmd___n___width 8
-#define reg_iop_dmc_out_rw_stream_cmd_offset 12
-
-/* Register rs_stream_data, scope iop_dmc_out, type rs */
-#define reg_iop_dmc_out_rs_stream_data_offset 16
-
-/* Register r_stream_data, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_data_offset 20
-
-/* Register r_stream_stat, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_stream_stat___dth___lsb 0
-#define reg_iop_dmc_out_r_stream_stat___dth___width 7
-#define reg_iop_dmc_out_r_stream_stat___dv___lsb 16
-#define reg_iop_dmc_out_r_stream_stat___dv___width 1
-#define reg_iop_dmc_out_r_stream_stat___dv___bit 16
-#define reg_iop_dmc_out_r_stream_stat___all_avail___lsb 17
-#define reg_iop_dmc_out_r_stream_stat___all_avail___width 1
-#define reg_iop_dmc_out_r_stream_stat___all_avail___bit 17
-#define reg_iop_dmc_out_r_stream_stat___last___lsb 18
-#define reg_iop_dmc_out_r_stream_stat___last___width 1
-#define reg_iop_dmc_out_r_stream_stat___last___bit 18
-#define reg_iop_dmc_out_r_stream_stat___size___lsb 19
-#define reg_iop_dmc_out_r_stream_stat___size___width 3
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___lsb 22
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___data_md_valid___bit 22
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___lsb 23
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___ctxt_md_valid___bit 23
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___lsb 24
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___width 1
-#define reg_iop_dmc_out_r_stream_stat___group_md_valid___bit 24
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___lsb 25
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___width 1
-#define reg_iop_dmc_out_r_stream_stat___stream_busy___bit 25
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___lsb 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rdy___bit 26
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___lsb 27
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___width 1
-#define reg_iop_dmc_out_r_stream_stat___cmd_rq___bit 27
-#define reg_iop_dmc_out_r_stream_stat_offset 24
-
-/* Register r_data_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_data_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_data_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_data_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_data_descr___stat___width 8
-#define reg_iop_dmc_out_r_data_descr___md___lsb 16
-#define reg_iop_dmc_out_r_data_descr___md___width 16
-#define reg_iop_dmc_out_r_data_descr_offset 28
-
-/* Register r_ctxt_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_ctxt_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_ctxt_descr___stat___width 8
-#define reg_iop_dmc_out_r_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_r_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_r_ctxt_descr_offset 32
-
-/* Register r_ctxt_descr_md1, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md1_offset 36
-
-/* Register r_ctxt_descr_md2, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_ctxt_descr_md2_offset 40
-
-/* Register r_group_descr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_group_descr___ctrl___lsb 0
-#define reg_iop_dmc_out_r_group_descr___ctrl___width 8
-#define reg_iop_dmc_out_r_group_descr___stat___lsb 8
-#define reg_iop_dmc_out_r_group_descr___stat___width 8
-#define reg_iop_dmc_out_r_group_descr___md___lsb 16
-#define reg_iop_dmc_out_r_group_descr___md___width 16
-#define reg_iop_dmc_out_r_group_descr_offset 52
-
-/* Register rw_data_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_data_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_data_descr___md___width 16
-#define reg_iop_dmc_out_rw_data_descr_offset 56
-
-/* Register rw_ctxt_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___lsb 16
-#define reg_iop_dmc_out_rw_ctxt_descr___md0___width 16
-#define reg_iop_dmc_out_rw_ctxt_descr_offset 60
-
-/* Register rw_ctxt_descr_md1, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md1_offset 64
-
-/* Register rw_ctxt_descr_md2, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ctxt_descr_md2_offset 68
-
-/* Register rw_group_descr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_group_descr___md___lsb 16
-#define reg_iop_dmc_out_rw_group_descr___md___width 16
-#define reg_iop_dmc_out_rw_group_descr_offset 80
-
-/* Register rw_intr_mask, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_intr_mask___data_md___lsb 0
-#define reg_iop_dmc_out_rw_intr_mask___data_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___data_md___bit 0
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___lsb 2
-#define reg_iop_dmc_out_rw_intr_mask___group_md___width 1
-#define reg_iop_dmc_out_rw_intr_mask___group_md___bit 2
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_intr_mask___dth___lsb 4
-#define reg_iop_dmc_out_rw_intr_mask___dth___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dth___bit 4
-#define reg_iop_dmc_out_rw_intr_mask___dv___lsb 5
-#define reg_iop_dmc_out_rw_intr_mask___dv___width 1
-#define reg_iop_dmc_out_rw_intr_mask___dv___bit 5
-#define reg_iop_dmc_out_rw_intr_mask___last_data___lsb 6
-#define reg_iop_dmc_out_rw_intr_mask___last_data___width 1
-#define reg_iop_dmc_out_rw_intr_mask___last_data___bit 6
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___width 1
-#define reg_iop_dmc_out_rw_intr_mask___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_intr_mask___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_intr_mask_offset 84
-
-/* Register rw_ack_intr, scope iop_dmc_out, type rw */
-#define reg_iop_dmc_out_rw_ack_intr___data_md___lsb 0
-#define reg_iop_dmc_out_rw_ack_intr___data_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___data_md___bit 0
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___lsb 2
-#define reg_iop_dmc_out_rw_ack_intr___group_md___width 1
-#define reg_iop_dmc_out_rw_ack_intr___group_md___bit 2
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_rw_ack_intr___dth___lsb 4
-#define reg_iop_dmc_out_rw_ack_intr___dth___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dth___bit 4
-#define reg_iop_dmc_out_rw_ack_intr___dv___lsb 5
-#define reg_iop_dmc_out_rw_ack_intr___dv___width 1
-#define reg_iop_dmc_out_rw_ack_intr___dv___bit 5
-#define reg_iop_dmc_out_rw_ack_intr___last_data___lsb 6
-#define reg_iop_dmc_out_rw_ack_intr___last_data___width 1
-#define reg_iop_dmc_out_rw_ack_intr___last_data___bit 6
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___width 1
-#define reg_iop_dmc_out_rw_ack_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_rw_ack_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_rw_ack_intr_offset 88
-
-/* Register r_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_intr___data_md___width 1
-#define reg_iop_dmc_out_r_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_intr___group_md___width 1
-#define reg_iop_dmc_out_r_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_intr___dth___width 1
-#define reg_iop_dmc_out_r_intr___dth___bit 4
-#define reg_iop_dmc_out_r_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_intr___dv___width 1
-#define reg_iop_dmc_out_r_intr___dv___bit 5
-#define reg_iop_dmc_out_r_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_intr___last_data___width 1
-#define reg_iop_dmc_out_r_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_intr_offset 92
-
-/* Register r_masked_intr, scope iop_dmc_out, type r */
-#define reg_iop_dmc_out_r_masked_intr___data_md___lsb 0
-#define reg_iop_dmc_out_r_masked_intr___data_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___data_md___bit 0
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___lsb 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___ctxt_md___bit 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___lsb 2
-#define reg_iop_dmc_out_r_masked_intr___group_md___width 1
-#define reg_iop_dmc_out_r_masked_intr___group_md___bit 2
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___lsb 3
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rdy___bit 3
-#define reg_iop_dmc_out_r_masked_intr___dth___lsb 4
-#define reg_iop_dmc_out_r_masked_intr___dth___width 1
-#define reg_iop_dmc_out_r_masked_intr___dth___bit 4
-#define reg_iop_dmc_out_r_masked_intr___dv___lsb 5
-#define reg_iop_dmc_out_r_masked_intr___dv___width 1
-#define reg_iop_dmc_out_r_masked_intr___dv___bit 5
-#define reg_iop_dmc_out_r_masked_intr___last_data___lsb 6
-#define reg_iop_dmc_out_r_masked_intr___last_data___width 1
-#define reg_iop_dmc_out_r_masked_intr___last_data___bit 6
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___lsb 7
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___width 1
-#define reg_iop_dmc_out_r_masked_intr___trf_lim___bit 7
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___lsb 8
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___width 1
-#define reg_iop_dmc_out_r_masked_intr___cmd_rq___bit 8
-#define reg_iop_dmc_out_r_masked_intr_offset 96
-
-
-/* Constants */
-#define regk_iop_dmc_out_ack_pkt                  0x00000100
-#define regk_iop_dmc_out_array                    0x00000008
-#define regk_iop_dmc_out_burst                    0x00000020
-#define regk_iop_dmc_out_copy_next                0x00000010
-#define regk_iop_dmc_out_copy_up                  0x00000020
-#define regk_iop_dmc_out_dis_c                    0x00000010
-#define regk_iop_dmc_out_dis_g                    0x00000020
-#define regk_iop_dmc_out_lim1                     0x00000000
-#define regk_iop_dmc_out_lim16                    0x00000004
-#define regk_iop_dmc_out_lim2                     0x00000001
-#define regk_iop_dmc_out_lim32                    0x00000005
-#define regk_iop_dmc_out_lim4                     0x00000002
-#define regk_iop_dmc_out_lim64                    0x00000006
-#define regk_iop_dmc_out_lim8                     0x00000003
-#define regk_iop_dmc_out_load_c                   0x00000200
-#define regk_iop_dmc_out_load_c_n                 0x00000280
-#define regk_iop_dmc_out_load_c_next              0x00000240
-#define regk_iop_dmc_out_load_d                   0x00000140
-#define regk_iop_dmc_out_load_g                   0x00000300
-#define regk_iop_dmc_out_load_g_down              0x000003c0
-#define regk_iop_dmc_out_load_g_next              0x00000340
-#define regk_iop_dmc_out_load_g_up                0x00000380
-#define regk_iop_dmc_out_next_en                  0x00000010
-#define regk_iop_dmc_out_next_pkt                 0x00000010
-#define regk_iop_dmc_out_no                       0x00000000
-#define regk_iop_dmc_out_restore                  0x00000020
-#define regk_iop_dmc_out_rw_cfg_default           0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_default    0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md1_default  0x00000000
-#define regk_iop_dmc_out_rw_ctxt_descr_md2_default  0x00000000
-#define regk_iop_dmc_out_rw_data_descr_default    0x00000000
-#define regk_iop_dmc_out_rw_group_descr_default   0x00000000
-#define regk_iop_dmc_out_rw_intr_mask_default     0x00000000
-#define regk_iop_dmc_out_save_down                0x00000020
-#define regk_iop_dmc_out_save_up                  0x00000020
-#define regk_iop_dmc_out_set_reg                  0x00000050
-#define regk_iop_dmc_out_set_w_size1              0x00000190
-#define regk_iop_dmc_out_set_w_size2              0x000001a0
-#define regk_iop_dmc_out_set_w_size4              0x000001c0
-#define regk_iop_dmc_out_store_c                  0x00000002
-#define regk_iop_dmc_out_store_descr              0x00000000
-#define regk_iop_dmc_out_store_g                  0x00000004
-#define regk_iop_dmc_out_store_md                 0x00000001
-#define regk_iop_dmc_out_update_down              0x00000020
-#define regk_iop_dmc_out_yes                      0x00000001
-#endif /* __iop_dmc_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h
deleted file mode 100644
index e2c0990246f2..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_defs_asm.h
+++ /dev/null
@@ -1,235 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_defs_asm_h
-#define __iop_fifo_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_in.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:07 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in.r
- *      id: $Id: iop_fifo_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_cfg___avail_lim___lsb 0
-#define reg_iop_fifo_in_rw_cfg___avail_lim___width 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_in_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_in_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_in_rw_cfg___trig___width 2
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_in_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_in_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_in_rw_cfg___mode___width 2
-#define reg_iop_fifo_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_in_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_r_stat___last___lsb 4
-#define reg_iop_fifo_in_r_stat___last___width 8
-#define reg_iop_fifo_in_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_r_stat_offset 8
-
-/* Register rs_rd1byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd1byte___data___width 8
-#define reg_iop_fifo_in_rs_rd1byte_offset 12
-
-/* Register r_rd1byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd1byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd1byte___data___width 8
-#define reg_iop_fifo_in_r_rd1byte_offset 16
-
-/* Register rs_rd2byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd2byte___data___width 16
-#define reg_iop_fifo_in_rs_rd2byte_offset 20
-
-/* Register r_rd2byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd2byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd2byte___data___width 16
-#define reg_iop_fifo_in_r_rd2byte_offset 24
-
-/* Register rs_rd3byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd3byte___data___width 24
-#define reg_iop_fifo_in_rs_rd3byte_offset 28
-
-/* Register r_rd3byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd3byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd3byte___data___width 24
-#define reg_iop_fifo_in_r_rd3byte_offset 32
-
-/* Register rs_rd4byte, scope iop_fifo_in, type rs */
-#define reg_iop_fifo_in_rs_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_rs_rd4byte___data___width 32
-#define reg_iop_fifo_in_rs_rd4byte_offset 36
-
-/* Register r_rd4byte, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_rd4byte___data___lsb 0
-#define reg_iop_fifo_in_r_rd4byte___data___width 32
-#define reg_iop_fifo_in_r_rd4byte_offset 40
-
-/* Register rw_set_last, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_set_last_offset 44
-
-/* Register rw_strb_dif_in, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_rw_strb_dif_in_offset 48
-
-/* Register rw_intr_mask, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_rw_intr_mask_offset 52
-
-/* Register rw_ack_intr, scope iop_fifo_in, type rw */
-#define reg_iop_fifo_in_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_rw_ack_intr_offset 56
-
-/* Register r_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_intr___urun___width 1
-#define reg_iop_fifo_in_r_intr___urun___bit 0
-#define reg_iop_fifo_in_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_intr___last_data___width 1
-#define reg_iop_fifo_in_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_intr___dav___width 1
-#define reg_iop_fifo_in_r_intr___dav___bit 2
-#define reg_iop_fifo_in_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_intr___avail___width 1
-#define reg_iop_fifo_in_r_intr___avail___bit 3
-#define reg_iop_fifo_in_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_intr___orun___width 1
-#define reg_iop_fifo_in_r_intr___orun___bit 4
-#define reg_iop_fifo_in_r_intr_offset 60
-
-/* Register r_masked_intr, scope iop_fifo_in, type r */
-#define reg_iop_fifo_in_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_r_masked_intr_offset 64
-
-
-/* Constants */
-#define regk_iop_fifo_in_dif_in                   0x00000002
-#define regk_iop_fifo_in_hi                       0x00000000
-#define regk_iop_fifo_in_neg                      0x00000002
-#define regk_iop_fifo_in_no                       0x00000000
-#define regk_iop_fifo_in_order16                  0x00000001
-#define regk_iop_fifo_in_order24                  0x00000002
-#define regk_iop_fifo_in_order32                  0x00000003
-#define regk_iop_fifo_in_order8                   0x00000000
-#define regk_iop_fifo_in_pos                      0x00000001
-#define regk_iop_fifo_in_pos_neg                  0x00000003
-#define regk_iop_fifo_in_rw_cfg_default           0x00000024
-#define regk_iop_fifo_in_rw_ctrl_default          0x00000000
-#define regk_iop_fifo_in_rw_intr_mask_default     0x00000000
-#define regk_iop_fifo_in_rw_set_last_default      0x00000000
-#define regk_iop_fifo_in_rw_strb_dif_in_default   0x00000000
-#define regk_iop_fifo_in_size16                   0x00000002
-#define regk_iop_fifo_in_size24                   0x00000001
-#define regk_iop_fifo_in_size32                   0x00000000
-#define regk_iop_fifo_in_size8                    0x00000003
-#define regk_iop_fifo_in_yes                      0x00000001
-#endif /* __iop_fifo_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
deleted file mode 100644
index 50837b989c90..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_in_extra_defs_asm.h
+++ /dev/null
@@ -1,156 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_in_extra_defs_asm_h
-#define __iop_fifo_in_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:08 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_in_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_in_extra.r
- *      id: $Id: iop_fifo_in_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_wr_data, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_wr_data_offset 0
-
-/* Register r_stat, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_in_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_in_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_in_extra_r_stat___last___width 8
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_in_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_in_extra_r_stat_offset 4
-
-/* Register rw_strb_dif_in, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___lsb 0
-#define reg_iop_fifo_in_extra_rw_strb_dif_in___last___width 2
-#define reg_iop_fifo_in_extra_rw_strb_dif_in_offset 8
-
-/* Register rw_intr_mask, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_in_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_intr_mask_offset 12
-
-/* Register rw_ack_intr, scope iop_fifo_in_extra, type rw */
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_in_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_rw_ack_intr_offset 16
-
-/* Register r_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_intr_offset 20
-
-/* Register r_masked_intr, scope iop_fifo_in_extra, type r */
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___lsb 3
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___avail___bit 3
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_in_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_in_extra_r_masked_intr_offset 24
-
-
-/* Constants */
-#define regk_iop_fifo_in_extra_fifo_in            0x00000002
-#define regk_iop_fifo_in_extra_no                 0x00000000
-#define regk_iop_fifo_in_extra_rw_intr_mask_default  0x00000000
-#define regk_iop_fifo_in_extra_yes                0x00000001
-#endif /* __iop_fifo_in_extra_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h
deleted file mode 100644
index 9f06dddf33a0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_defs_asm.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_defs_asm_h
-#define __iop_fifo_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_out.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:09 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out.r
- *      id: $Id: iop_fifo_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_cfg___free_lim___lsb 0
-#define reg_iop_fifo_out_rw_cfg___free_lim___width 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___lsb 3
-#define reg_iop_fifo_out_rw_cfg___byte_order___width 2
-#define reg_iop_fifo_out_rw_cfg___trig___lsb 5
-#define reg_iop_fifo_out_rw_cfg___trig___width 2
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___lsb 7
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_in___bit 7
-#define reg_iop_fifo_out_rw_cfg___mode___lsb 8
-#define reg_iop_fifo_out_rw_cfg___mode___width 2
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___lsb 10
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___width 1
-#define reg_iop_fifo_out_rw_cfg___delay_out_last___bit 10
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___lsb 11
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___width 1
-#define reg_iop_fifo_out_rw_cfg___last_dis_dif_out___bit 11
-#define reg_iop_fifo_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___lsb 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___width 1
-#define reg_iop_fifo_out_rw_ctrl___dif_out_en___bit 1
-#define reg_iop_fifo_out_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_r_stat___last___lsb 4
-#define reg_iop_fifo_out_r_stat___last___width 8
-#define reg_iop_fifo_out_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_r_stat_offset 8
-
-/* Register rw_wr1byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_offset 12
-
-/* Register rw_wr2byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_offset 16
-
-/* Register rw_wr3byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_offset 20
-
-/* Register rw_wr4byte, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_offset 24
-
-/* Register rw_wr1byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr1byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr1byte_last___data___width 8
-#define reg_iop_fifo_out_rw_wr1byte_last_offset 28
-
-/* Register rw_wr2byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr2byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr2byte_last___data___width 16
-#define reg_iop_fifo_out_rw_wr2byte_last_offset 32
-
-/* Register rw_wr3byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr3byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr3byte_last___data___width 24
-#define reg_iop_fifo_out_rw_wr3byte_last_offset 36
-
-/* Register rw_wr4byte_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_wr4byte_last___data___lsb 0
-#define reg_iop_fifo_out_rw_wr4byte_last___data___width 32
-#define reg_iop_fifo_out_rw_wr4byte_last_offset 40
-
-/* Register rw_set_last, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_set_last_offset 44
-
-/* Register rs_rd_data, scope iop_fifo_out, type rs */
-#define reg_iop_fifo_out_rs_rd_data_offset 48
-
-/* Register r_rd_data, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_rd_data_offset 52
-
-/* Register rw_strb_dif_out, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_strb_dif_out_offset 56
-
-/* Register rw_intr_mask, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_rw_intr_mask_offset 60
-
-/* Register rw_ack_intr, scope iop_fifo_out, type rw */
-#define reg_iop_fifo_out_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_rw_ack_intr_offset 64
-
-/* Register r_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_intr___urun___width 1
-#define reg_iop_fifo_out_r_intr___urun___bit 0
-#define reg_iop_fifo_out_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_intr___last_data___width 1
-#define reg_iop_fifo_out_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_intr___dav___width 1
-#define reg_iop_fifo_out_r_intr___dav___bit 2
-#define reg_iop_fifo_out_r_intr___free___lsb 3
-#define reg_iop_fifo_out_r_intr___free___width 1
-#define reg_iop_fifo_out_r_intr___free___bit 3
-#define reg_iop_fifo_out_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_intr___orun___width 1
-#define reg_iop_fifo_out_r_intr___orun___bit 4
-#define reg_iop_fifo_out_r_intr_offset 68
-
-/* Register r_masked_intr, scope iop_fifo_out, type r */
-#define reg_iop_fifo_out_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_r_masked_intr_offset 72
-
-
-/* Constants */
-#define regk_iop_fifo_out_hi                      0x00000000
-#define regk_iop_fifo_out_neg                     0x00000002
-#define regk_iop_fifo_out_no                      0x00000000
-#define regk_iop_fifo_out_order16                 0x00000001
-#define regk_iop_fifo_out_order24                 0x00000002
-#define regk_iop_fifo_out_order32                 0x00000003
-#define regk_iop_fifo_out_order8                  0x00000000
-#define regk_iop_fifo_out_pos                     0x00000001
-#define regk_iop_fifo_out_pos_neg                 0x00000003
-#define regk_iop_fifo_out_rw_cfg_default          0x00000024
-#define regk_iop_fifo_out_rw_ctrl_default         0x00000000
-#define regk_iop_fifo_out_rw_intr_mask_default    0x00000000
-#define regk_iop_fifo_out_rw_set_last_default     0x00000000
-#define regk_iop_fifo_out_rw_strb_dif_out_default  0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr1byte_last_default  0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr2byte_last_default  0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr3byte_last_default  0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_default      0x00000000
-#define regk_iop_fifo_out_rw_wr4byte_last_default  0x00000000
-#define regk_iop_fifo_out_size16                  0x00000002
-#define regk_iop_fifo_out_size24                  0x00000001
-#define regk_iop_fifo_out_size32                  0x00000000
-#define regk_iop_fifo_out_size8                   0x00000003
-#define regk_iop_fifo_out_yes                     0x00000001
-#endif /* __iop_fifo_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
deleted file mode 100644
index e8c488c389e4..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_fifo_out_extra_defs_asm.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_fifo_out_extra_defs_asm_h
-#define __iop_fifo_out_extra_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:10 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_fifo_out_extra_defs_asm.h ../../inst/io_proc/rtl/iop_fifo_out_extra.r
- *      id: $Id: iop_fifo_out_extra_defs_asm.h,v 1.1 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rs_rd_data, scope iop_fifo_out_extra, type rs */
-#define reg_iop_fifo_out_extra_rs_rd_data_offset 0
-
-/* Register r_rd_data, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_rd_data_offset 4
-
-/* Register r_stat, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___lsb 0
-#define reg_iop_fifo_out_extra_r_stat___avail_bytes___width 4
-#define reg_iop_fifo_out_extra_r_stat___last___lsb 4
-#define reg_iop_fifo_out_extra_r_stat___last___width 8
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___lsb 12
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_in_en___bit 12
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___lsb 13
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___width 1
-#define reg_iop_fifo_out_extra_r_stat___dif_out_en___bit 13
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___lsb 14
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___width 1
-#define reg_iop_fifo_out_extra_r_stat___zero_data_last___bit 14
-#define reg_iop_fifo_out_extra_r_stat_offset 8
-
-/* Register rw_strb_dif_out, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_strb_dif_out_offset 12
-
-/* Register rw_intr_mask, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___free___bit 3
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___width 1
-#define reg_iop_fifo_out_extra_rw_intr_mask___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_intr_mask_offset 16
-
-/* Register rw_ack_intr, scope iop_fifo_out_extra, type rw */
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___free___bit 3
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___width 1
-#define reg_iop_fifo_out_extra_rw_ack_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_rw_ack_intr_offset 20
-
-/* Register r_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_intr_offset 24
-
-/* Register r_masked_intr, scope iop_fifo_out_extra, type r */
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___lsb 0
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___urun___bit 0
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___lsb 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___last_data___bit 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___lsb 2
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___dav___bit 2
-#define reg_iop_fifo_out_extra_r_masked_intr___free___lsb 3
-#define reg_iop_fifo_out_extra_r_masked_intr___free___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___free___bit 3
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___lsb 4
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___width 1
-#define reg_iop_fifo_out_extra_r_masked_intr___orun___bit 4
-#define reg_iop_fifo_out_extra_r_masked_intr_offset 28
-
-
-/* Constants */
-#define regk_iop_fifo_out_extra_no                0x00000000
-#define regk_iop_fifo_out_extra_rw_intr_mask_default  0x00000000
-#define regk_iop_fifo_out_extra_yes               0x00000001
-#endif /* __iop_fifo_out_extra_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h
deleted file mode 100644
index 48869d445e07..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_mpu_defs_asm.h
+++ /dev/null
@@ -1,178 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_mpu_defs_asm_h
-#define __iop_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_mpu.r
- *     id:           iop_mpu.r,v 1.30 2005/02/17 08:12:33 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_mpu_defs_asm.h ../../inst/io_proc/rtl/iop_mpu.r
- *      id: $Id: iop_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_mpu_rw_r 4
-/* Register rw_r, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_r_offset 0
-
-/* Register rw_ctrl, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_ctrl___en___lsb 0
-#define reg_iop_mpu_rw_ctrl___en___width 1
-#define reg_iop_mpu_rw_ctrl___en___bit 0
-#define reg_iop_mpu_rw_ctrl_offset 128
-
-/* Register r_pc, scope iop_mpu, type r */
-#define reg_iop_mpu_r_pc___addr___lsb 0
-#define reg_iop_mpu_r_pc___addr___width 12
-#define reg_iop_mpu_r_pc_offset 132
-
-/* Register r_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_stat___instr_reg_busy___lsb 0
-#define reg_iop_mpu_r_stat___instr_reg_busy___width 1
-#define reg_iop_mpu_r_stat___instr_reg_busy___bit 0
-#define reg_iop_mpu_r_stat___intr_busy___lsb 1
-#define reg_iop_mpu_r_stat___intr_busy___width 1
-#define reg_iop_mpu_r_stat___intr_busy___bit 1
-#define reg_iop_mpu_r_stat___intr_vect___lsb 2
-#define reg_iop_mpu_r_stat___intr_vect___width 16
-#define reg_iop_mpu_r_stat_offset 136
-
-/* Register rw_instr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_instr_offset 140
-
-/* Register rw_immediate, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_immediate_offset 144
-
-/* Register r_trace, scope iop_mpu, type r */
-#define reg_iop_mpu_r_trace___intr_vect___lsb 0
-#define reg_iop_mpu_r_trace___intr_vect___width 16
-#define reg_iop_mpu_r_trace___pc___lsb 16
-#define reg_iop_mpu_r_trace___pc___width 12
-#define reg_iop_mpu_r_trace___en___lsb 28
-#define reg_iop_mpu_r_trace___en___width 1
-#define reg_iop_mpu_r_trace___en___bit 28
-#define reg_iop_mpu_r_trace___instr_reg_busy___lsb 29
-#define reg_iop_mpu_r_trace___instr_reg_busy___width 1
-#define reg_iop_mpu_r_trace___instr_reg_busy___bit 29
-#define reg_iop_mpu_r_trace___intr_busy___lsb 30
-#define reg_iop_mpu_r_trace___intr_busy___width 1
-#define reg_iop_mpu_r_trace___intr_busy___bit 30
-#define reg_iop_mpu_r_trace_offset 148
-
-/* Register r_wr_stat, scope iop_mpu, type r */
-#define reg_iop_mpu_r_wr_stat___r0___lsb 0
-#define reg_iop_mpu_r_wr_stat___r0___width 1
-#define reg_iop_mpu_r_wr_stat___r0___bit 0
-#define reg_iop_mpu_r_wr_stat___r1___lsb 1
-#define reg_iop_mpu_r_wr_stat___r1___width 1
-#define reg_iop_mpu_r_wr_stat___r1___bit 1
-#define reg_iop_mpu_r_wr_stat___r2___lsb 2
-#define reg_iop_mpu_r_wr_stat___r2___width 1
-#define reg_iop_mpu_r_wr_stat___r2___bit 2
-#define reg_iop_mpu_r_wr_stat___r3___lsb 3
-#define reg_iop_mpu_r_wr_stat___r3___width 1
-#define reg_iop_mpu_r_wr_stat___r3___bit 3
-#define reg_iop_mpu_r_wr_stat___r4___lsb 4
-#define reg_iop_mpu_r_wr_stat___r4___width 1
-#define reg_iop_mpu_r_wr_stat___r4___bit 4
-#define reg_iop_mpu_r_wr_stat___r5___lsb 5
-#define reg_iop_mpu_r_wr_stat___r5___width 1
-#define reg_iop_mpu_r_wr_stat___r5___bit 5
-#define reg_iop_mpu_r_wr_stat___r6___lsb 6
-#define reg_iop_mpu_r_wr_stat___r6___width 1
-#define reg_iop_mpu_r_wr_stat___r6___bit 6
-#define reg_iop_mpu_r_wr_stat___r7___lsb 7
-#define reg_iop_mpu_r_wr_stat___r7___width 1
-#define reg_iop_mpu_r_wr_stat___r7___bit 7
-#define reg_iop_mpu_r_wr_stat___r8___lsb 8
-#define reg_iop_mpu_r_wr_stat___r8___width 1
-#define reg_iop_mpu_r_wr_stat___r8___bit 8
-#define reg_iop_mpu_r_wr_stat___r9___lsb 9
-#define reg_iop_mpu_r_wr_stat___r9___width 1
-#define reg_iop_mpu_r_wr_stat___r9___bit 9
-#define reg_iop_mpu_r_wr_stat___r10___lsb 10
-#define reg_iop_mpu_r_wr_stat___r10___width 1
-#define reg_iop_mpu_r_wr_stat___r10___bit 10
-#define reg_iop_mpu_r_wr_stat___r11___lsb 11
-#define reg_iop_mpu_r_wr_stat___r11___width 1
-#define reg_iop_mpu_r_wr_stat___r11___bit 11
-#define reg_iop_mpu_r_wr_stat___r12___lsb 12
-#define reg_iop_mpu_r_wr_stat___r12___width 1
-#define reg_iop_mpu_r_wr_stat___r12___bit 12
-#define reg_iop_mpu_r_wr_stat___r13___lsb 13
-#define reg_iop_mpu_r_wr_stat___r13___width 1
-#define reg_iop_mpu_r_wr_stat___r13___bit 13
-#define reg_iop_mpu_r_wr_stat___r14___lsb 14
-#define reg_iop_mpu_r_wr_stat___r14___width 1
-#define reg_iop_mpu_r_wr_stat___r14___bit 14
-#define reg_iop_mpu_r_wr_stat___r15___lsb 15
-#define reg_iop_mpu_r_wr_stat___r15___width 1
-#define reg_iop_mpu_r_wr_stat___r15___bit 15
-#define reg_iop_mpu_r_wr_stat_offset 152
-
-#define STRIDE_iop_mpu_rw_thread 4
-/* Register rw_thread, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_thread___addr___lsb 0
-#define reg_iop_mpu_rw_thread___addr___width 12
-#define reg_iop_mpu_rw_thread_offset 156
-
-#define STRIDE_iop_mpu_rw_intr 4
-/* Register rw_intr, scope iop_mpu, type rw */
-#define reg_iop_mpu_rw_intr___addr___lsb 0
-#define reg_iop_mpu_rw_intr___addr___width 12
-#define reg_iop_mpu_rw_intr_offset 196
-
-
-/* Constants */
-#define regk_iop_mpu_no                           0x00000000
-#define regk_iop_mpu_r_pc_default                 0x00000000
-#define regk_iop_mpu_rw_ctrl_default              0x00000000
-#define regk_iop_mpu_rw_intr_size                 0x00000010
-#define regk_iop_mpu_rw_r_size                    0x00000010
-#define regk_iop_mpu_rw_thread_default            0x00000000
-#define regk_iop_mpu_rw_thread_size               0x00000004
-#define regk_iop_mpu_yes                          0x00000001
-#endif /* __iop_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h
deleted file mode 100644
index 615f869a6de9..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_reg_space_asm.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/* Autogenerated Changes here will be lost!
- * generated by ../gen_sw.pl Mon Apr 11 16:10:18 2005 iop_sw.cfg
- */
-#define iop_version 0
-#define iop_fifo_in0_extra 64
-#define iop_fifo_in1_extra 128
-#define iop_fifo_out0_extra 192
-#define iop_fifo_out1_extra 256
-#define iop_trigger_grp0 320
-#define iop_trigger_grp1 384
-#define iop_trigger_grp2 448
-#define iop_trigger_grp3 512
-#define iop_trigger_grp4 576
-#define iop_trigger_grp5 640
-#define iop_trigger_grp6 704
-#define iop_trigger_grp7 768
-#define iop_crc_par0 896
-#define iop_crc_par1 1024
-#define iop_dmc_in0 1152
-#define iop_dmc_in1 1280
-#define iop_dmc_out0 1408
-#define iop_dmc_out1 1536
-#define iop_fifo_in0 1664
-#define iop_fifo_in1 1792
-#define iop_fifo_out0 1920
-#define iop_fifo_out1 2048
-#define iop_scrc_in0 2176
-#define iop_scrc_in1 2304
-#define iop_scrc_out0 2432
-#define iop_scrc_out1 2560
-#define iop_timer_grp0 2688
-#define iop_timer_grp1 2816
-#define iop_timer_grp2 2944
-#define iop_timer_grp3 3072
-#define iop_sap_in 3328
-#define iop_sap_out 3584
-#define iop_spu0 3840
-#define iop_spu1 4096
-#define iop_sw_cfg 4352
-#define iop_sw_cpu 4608
-#define iop_sw_mpu 4864
-#define iop_sw_spu0 5120
-#define iop_sw_spu1 5376
-#define iop_mpu 5632
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h
deleted file mode 100644
index fe8c90e015b0..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_in_defs_asm.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_in_defs_asm_h
-#define __iop_sap_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_sap_in.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:45 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_in_defs_asm.h ../../inst/io_proc/rtl/iop_sap_in.r
- *      id: $Id: iop_sap_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_bus0_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus0_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus0_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus0_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus0_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus0_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus0_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus0_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus0_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus0_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus0_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus0_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus0_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus0_sync_offset 0
-
-/* Register rw_bus1_sync, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___lsb 0
-#define reg_iop_sap_in_rw_bus1_sync___byte0_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___lsb 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___lsb 5
-#define reg_iop_sap_in_rw_bus1_sync___byte0_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___lsb 7
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte0_delay___bit 7
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___lsb 8
-#define reg_iop_sap_in_rw_bus1_sync___byte1_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___lsb 10
-#define reg_iop_sap_in_rw_bus1_sync___byte1_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___lsb 13
-#define reg_iop_sap_in_rw_bus1_sync___byte1_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___lsb 15
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte1_delay___bit 15
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___lsb 16
-#define reg_iop_sap_in_rw_bus1_sync___byte2_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___lsb 18
-#define reg_iop_sap_in_rw_bus1_sync___byte2_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___lsb 21
-#define reg_iop_sap_in_rw_bus1_sync___byte2_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___lsb 23
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte2_delay___bit 23
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___lsb 24
-#define reg_iop_sap_in_rw_bus1_sync___byte3_sel___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___lsb 26
-#define reg_iop_sap_in_rw_bus1_sync___byte3_ext_src___width 3
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___lsb 29
-#define reg_iop_sap_in_rw_bus1_sync___byte3_edge___width 2
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___lsb 31
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___width 1
-#define reg_iop_sap_in_rw_bus1_sync___byte3_delay___bit 31
-#define reg_iop_sap_in_rw_bus1_sync_offset 4
-
-#define STRIDE_iop_sap_in_rw_gio 4
-/* Register rw_gio, scope iop_sap_in, type rw */
-#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0
-#define reg_iop_sap_in_rw_gio___sync_sel___width 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2
-#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3
-#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5
-#define reg_iop_sap_in_rw_gio___sync_edge___width 2
-#define reg_iop_sap_in_rw_gio___delay___lsb 7
-#define reg_iop_sap_in_rw_gio___delay___width 1
-#define reg_iop_sap_in_rw_gio___delay___bit 7
-#define reg_iop_sap_in_rw_gio___logic___lsb 8
-#define reg_iop_sap_in_rw_gio___logic___width 2
-#define reg_iop_sap_in_rw_gio_offset 8
-
-
-/* Constants */
-#define regk_iop_sap_in_and                       0x00000002
-#define regk_iop_sap_in_ext_clk200                0x00000003
-#define regk_iop_sap_in_gio1                      0x00000000
-#define regk_iop_sap_in_gio13                     0x00000005
-#define regk_iop_sap_in_gio18                     0x00000003
-#define regk_iop_sap_in_gio19                     0x00000004
-#define regk_iop_sap_in_gio21                     0x00000006
-#define regk_iop_sap_in_gio23                     0x00000005
-#define regk_iop_sap_in_gio29                     0x00000007
-#define regk_iop_sap_in_gio5                      0x00000004
-#define regk_iop_sap_in_gio6                      0x00000001
-#define regk_iop_sap_in_gio7                      0x00000002
-#define regk_iop_sap_in_inv                       0x00000001
-#define regk_iop_sap_in_neg                       0x00000002
-#define regk_iop_sap_in_no                        0x00000000
-#define regk_iop_sap_in_no_del_ext_clk200         0x00000001
-#define regk_iop_sap_in_none                      0x00000000
-#define regk_iop_sap_in_or                        0x00000003
-#define regk_iop_sap_in_pos                       0x00000001
-#define regk_iop_sap_in_pos_neg                   0x00000003
-#define regk_iop_sap_in_rw_bus0_sync_default      0x02020202
-#define regk_iop_sap_in_rw_bus1_sync_default      0x02020202
-#define regk_iop_sap_in_rw_gio_default            0x00000002
-#define regk_iop_sap_in_rw_gio_size               0x00000020
-#define regk_iop_sap_in_timer_grp0_tmr3           0x00000006
-#define regk_iop_sap_in_timer_grp1_tmr3           0x00000004
-#define regk_iop_sap_in_timer_grp2_tmr3           0x00000005
-#define regk_iop_sap_in_timer_grp3_tmr3           0x00000007
-#define regk_iop_sap_in_tmr_clk200                0x00000000
-#define regk_iop_sap_in_two_clk200                0x00000002
-#define regk_iop_sap_in_yes                       0x00000001
-#endif /* __iop_sap_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h
deleted file mode 100644
index a5e46f0bbf6f..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sap_out_defs_asm.h
+++ /dev/null
@@ -1,347 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sap_out_defs_asm_h
-#define __iop_sap_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_sap_out.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sap_out_defs_asm.h ../../inst/io_proc/rtl/iop_sap_out.r
- *      id: $Id: iop_sap_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_gen_gated, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0
-#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4
-#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7
-#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9
-#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11
-#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___lsb 14
-#define reg_iop_sap_out_rw_gen_gated___clk2_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___lsb 16
-#define reg_iop_sap_out_rw_gen_gated___clk2_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___lsb 18
-#define reg_iop_sap_out_rw_gen_gated___clk2_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___lsb 21
-#define reg_iop_sap_out_rw_gen_gated___clk3_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___lsb 23
-#define reg_iop_sap_out_rw_gen_gated___clk3_gate_src___width 2
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___lsb 25
-#define reg_iop_sap_out_rw_gen_gated___clk3_force_src___width 3
-#define reg_iop_sap_out_rw_gen_gated_offset 0
-
-/* Register rw_bus0, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus0___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus0___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus0___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus0___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus0___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus0___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus0___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus0_offset 4
-
-/* Register rw_bus1, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___lsb 3
-#define reg_iop_sap_out_rw_bus1___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___lsb 5
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte0_clk_inv___bit 5
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___lsb 6
-#define reg_iop_sap_out_rw_bus1___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___lsb 9
-#define reg_iop_sap_out_rw_bus1___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___lsb 11
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte1_clk_inv___bit 11
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___lsb 12
-#define reg_iop_sap_out_rw_bus1___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___lsb 15
-#define reg_iop_sap_out_rw_bus1___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___lsb 17
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte2_clk_inv___bit 17
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___lsb 18
-#define reg_iop_sap_out_rw_bus1___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___lsb 21
-#define reg_iop_sap_out_rw_bus1___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___lsb 23
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1___byte3_clk_inv___bit 23
-#define reg_iop_sap_out_rw_bus1_offset 8
-
-/* Register rw_bus0_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus0_lo_oe_offset 12
-
-/* Register rw_bus0_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus0_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus0_hi_oe_offset 16
-
-/* Register rw_bus1_lo_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte0_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_lo_oe___byte1_logic___width 2
-#define reg_iop_sap_out_rw_bus1_lo_oe_offset 20
-
-/* Register rw_bus1_hi_oe, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___lsb 6
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___lsb 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_clk_inv___bit 8
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___lsb 9
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte2_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_sel___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_ext___width 3
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_gated_clk___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___width 1
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_clk_inv___bit 19
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___lsb 20
-#define reg_iop_sap_out_rw_bus1_hi_oe___byte3_logic___width 2
-#define reg_iop_sap_out_rw_bus1_hi_oe_offset 24
-
-#define STRIDE_iop_sap_out_rw_gio 4
-/* Register rw_gio, scope iop_sap_out, type rw */
-#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0
-#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3
-#define reg_iop_sap_out_rw_gio___out_clk_ext___width 4
-#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 7
-#define reg_iop_sap_out_rw_gio___out_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 9
-#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 9
-#define reg_iop_sap_out_rw_gio___out_logic___lsb 10
-#define reg_iop_sap_out_rw_gio___out_logic___width 1
-#define reg_iop_sap_out_rw_gio___out_logic___bit 10
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 11
-#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 14
-#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 3
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17
-#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 2
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 19
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1
-#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 19
-#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20
-#define reg_iop_sap_out_rw_gio___oe_logic___width 2
-#define reg_iop_sap_out_rw_gio_offset 28
-
-
-/* Constants */
-#define regk_iop_sap_out_and                      0x00000002
-#define regk_iop_sap_out_clk0                     0x00000000
-#define regk_iop_sap_out_clk1                     0x00000001
-#define regk_iop_sap_out_clk12                    0x00000002
-#define regk_iop_sap_out_clk2                     0x00000002
-#define regk_iop_sap_out_clk200                   0x00000001
-#define regk_iop_sap_out_clk3                     0x00000003
-#define regk_iop_sap_out_ext                      0x00000003
-#define regk_iop_sap_out_gated                    0x00000004
-#define regk_iop_sap_out_gio1                     0x00000000
-#define regk_iop_sap_out_gio13                    0x00000002
-#define regk_iop_sap_out_gio13_clk                0x0000000c
-#define regk_iop_sap_out_gio15                    0x00000001
-#define regk_iop_sap_out_gio18                    0x00000003
-#define regk_iop_sap_out_gio18_clk                0x0000000d
-#define regk_iop_sap_out_gio1_clk                 0x00000008
-#define regk_iop_sap_out_gio21_clk                0x0000000e
-#define regk_iop_sap_out_gio23                    0x00000002
-#define regk_iop_sap_out_gio29_clk                0x0000000f
-#define regk_iop_sap_out_gio31                    0x00000003
-#define regk_iop_sap_out_gio5                     0x00000001
-#define regk_iop_sap_out_gio5_clk                 0x00000009
-#define regk_iop_sap_out_gio6_clk                 0x0000000a
-#define regk_iop_sap_out_gio7                     0x00000000
-#define regk_iop_sap_out_gio7_clk                 0x0000000b
-#define regk_iop_sap_out_gio_in13                 0x00000001
-#define regk_iop_sap_out_gio_in21                 0x00000002
-#define regk_iop_sap_out_gio_in29                 0x00000003
-#define regk_iop_sap_out_gio_in5                  0x00000000
-#define regk_iop_sap_out_inv                      0x00000001
-#define regk_iop_sap_out_nand                     0x00000003
-#define regk_iop_sap_out_no                       0x00000000
-#define regk_iop_sap_out_none                     0x00000000
-#define regk_iop_sap_out_rw_bus0_default          0x00000000
-#define regk_iop_sap_out_rw_bus0_hi_oe_default    0x00000000
-#define regk_iop_sap_out_rw_bus0_lo_oe_default    0x00000000
-#define regk_iop_sap_out_rw_bus1_default          0x00000000
-#define regk_iop_sap_out_rw_bus1_hi_oe_default    0x00000000
-#define regk_iop_sap_out_rw_bus1_lo_oe_default    0x00000000
-#define regk_iop_sap_out_rw_gen_gated_default     0x00000000
-#define regk_iop_sap_out_rw_gio_default           0x00000000
-#define regk_iop_sap_out_rw_gio_size              0x00000020
-#define regk_iop_sap_out_spu0_gio0                0x00000002
-#define regk_iop_sap_out_spu0_gio1                0x00000003
-#define regk_iop_sap_out_spu0_gio12               0x00000004
-#define regk_iop_sap_out_spu0_gio13               0x00000004
-#define regk_iop_sap_out_spu0_gio14               0x00000004
-#define regk_iop_sap_out_spu0_gio15               0x00000004
-#define regk_iop_sap_out_spu0_gio2                0x00000002
-#define regk_iop_sap_out_spu0_gio3                0x00000003
-#define regk_iop_sap_out_spu0_gio4                0x00000002
-#define regk_iop_sap_out_spu0_gio5                0x00000003
-#define regk_iop_sap_out_spu0_gio6                0x00000002
-#define regk_iop_sap_out_spu0_gio7                0x00000003
-#define regk_iop_sap_out_spu1_gio0                0x00000005
-#define regk_iop_sap_out_spu1_gio1                0x00000006
-#define regk_iop_sap_out_spu1_gio12               0x00000007
-#define regk_iop_sap_out_spu1_gio13               0x00000007
-#define regk_iop_sap_out_spu1_gio14               0x00000007
-#define regk_iop_sap_out_spu1_gio15               0x00000007
-#define regk_iop_sap_out_spu1_gio2                0x00000005
-#define regk_iop_sap_out_spu1_gio3                0x00000006
-#define regk_iop_sap_out_spu1_gio4                0x00000005
-#define regk_iop_sap_out_spu1_gio5                0x00000006
-#define regk_iop_sap_out_spu1_gio6                0x00000005
-#define regk_iop_sap_out_spu1_gio7                0x00000006
-#define regk_iop_sap_out_timer_grp0_tmr2          0x00000004
-#define regk_iop_sap_out_timer_grp1_tmr2          0x00000005
-#define regk_iop_sap_out_timer_grp2_tmr2          0x00000006
-#define regk_iop_sap_out_timer_grp3_tmr2          0x00000007
-#define regk_iop_sap_out_tmr                      0x00000005
-#define regk_iop_sap_out_yes                      0x00000001
-#endif /* __iop_sap_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h
deleted file mode 100644
index 169aaf8d44b2..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_in_defs_asm.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_in_defs_asm_h
-#define __iop_scrc_in_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_scrc_in.r
- *     id:           iop_scrc_in.r,v 1.10 2005/02/16 09:13:58 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_in_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_in.r
- *      id: $Id: iop_scrc_in_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_in_rw_cfg___trig___width 2
-#define reg_iop_scrc_in_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___lsb 0
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___width 1
-#define reg_iop_scrc_in_rw_ctrl___dif_in_en___bit 0
-#define reg_iop_scrc_in_rw_ctrl_offset 4
-
-/* Register r_stat, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_stat___err___lsb 0
-#define reg_iop_scrc_in_r_stat___err___width 1
-#define reg_iop_scrc_in_r_stat___err___bit 0
-#define reg_iop_scrc_in_r_stat_offset 8
-
-/* Register rw_init_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_init_crc_offset 12
-
-/* Register rs_computed_crc, scope iop_scrc_in, type rs */
-#define reg_iop_scrc_in_rs_computed_crc_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_in, type r */
-#define reg_iop_scrc_in_r_computed_crc_offset 20
-
-/* Register rw_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_crc_offset 24
-
-/* Register rw_correct_crc, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_correct_crc_offset 28
-
-/* Register rw_wr1bit, scope iop_scrc_in, type rw */
-#define reg_iop_scrc_in_rw_wr1bit___data___lsb 0
-#define reg_iop_scrc_in_rw_wr1bit___data___width 2
-#define reg_iop_scrc_in_rw_wr1bit___last___lsb 2
-#define reg_iop_scrc_in_rw_wr1bit___last___width 2
-#define reg_iop_scrc_in_rw_wr1bit_offset 32
-
-
-/* Constants */
-#define regk_iop_scrc_in_dif_in                   0x00000002
-#define regk_iop_scrc_in_hi                       0x00000000
-#define regk_iop_scrc_in_neg                      0x00000002
-#define regk_iop_scrc_in_no                       0x00000000
-#define regk_iop_scrc_in_pos                      0x00000001
-#define regk_iop_scrc_in_pos_neg                  0x00000003
-#define regk_iop_scrc_in_r_computed_crc_default   0x00000000
-#define regk_iop_scrc_in_rs_computed_crc_default  0x00000000
-#define regk_iop_scrc_in_rw_cfg_default           0x00000000
-#define regk_iop_scrc_in_rw_ctrl_default          0x00000000
-#define regk_iop_scrc_in_rw_init_crc_default      0x00000000
-#define regk_iop_scrc_in_set0                     0x00000000
-#define regk_iop_scrc_in_set1                     0x00000001
-#define regk_iop_scrc_in_yes                      0x00000001
-#endif /* __iop_scrc_in_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h
deleted file mode 100644
index 0e9bca149bc6..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_scrc_out_defs_asm.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_scrc_out_defs_asm_h
-#define __iop_scrc_out_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_scrc_out.r
- *     id:           iop_scrc_out.r,v 1.11 2005/02/16 09:13:38 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_scrc_out_defs_asm.h ../../inst/io_proc/rtl/iop_scrc_out.r
- *      id: $Id: iop_scrc_out_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_cfg___trig___lsb 0
-#define reg_iop_scrc_out_rw_cfg___trig___width 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___lsb 2
-#define reg_iop_scrc_out_rw_cfg___inv_crc___width 1
-#define reg_iop_scrc_out_rw_cfg___inv_crc___bit 2
-#define reg_iop_scrc_out_rw_cfg_offset 0
-
-/* Register rw_ctrl, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_ctrl___strb_src___lsb 0
-#define reg_iop_scrc_out_rw_ctrl___strb_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___strb_src___bit 0
-#define reg_iop_scrc_out_rw_ctrl___out_src___lsb 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___width 1
-#define reg_iop_scrc_out_rw_ctrl___out_src___bit 1
-#define reg_iop_scrc_out_rw_ctrl_offset 4
-
-/* Register rw_init_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_init_crc_offset 8
-
-/* Register rw_crc, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_crc_offset 12
-
-/* Register rw_data, scope iop_scrc_out, type rw */
-#define reg_iop_scrc_out_rw_data___val___lsb 0
-#define reg_iop_scrc_out_rw_data___val___width 1
-#define reg_iop_scrc_out_rw_data___val___bit 0
-#define reg_iop_scrc_out_rw_data_offset 16
-
-/* Register r_computed_crc, scope iop_scrc_out, type r */
-#define reg_iop_scrc_out_r_computed_crc_offset 20
-
-
-/* Constants */
-#define regk_iop_scrc_out_crc                     0x00000001
-#define regk_iop_scrc_out_data                    0x00000000
-#define regk_iop_scrc_out_dif                     0x00000001
-#define regk_iop_scrc_out_hi                      0x00000000
-#define regk_iop_scrc_out_neg                     0x00000002
-#define regk_iop_scrc_out_no                      0x00000000
-#define regk_iop_scrc_out_pos                     0x00000001
-#define regk_iop_scrc_out_pos_neg                 0x00000003
-#define regk_iop_scrc_out_reg                     0x00000000
-#define regk_iop_scrc_out_rw_cfg_default          0x00000000
-#define regk_iop_scrc_out_rw_crc_default          0x00000000
-#define regk_iop_scrc_out_rw_ctrl_default         0x00000000
-#define regk_iop_scrc_out_rw_data_default         0x00000000
-#define regk_iop_scrc_out_rw_init_crc_default     0x00000000
-#define regk_iop_scrc_out_yes                     0x00000001
-#endif /* __iop_scrc_out_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h
deleted file mode 100644
index cf2b64a9d42c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_spu_defs_asm.h
+++ /dev/null
@@ -1,574 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_spu_defs_asm_h
-#define __iop_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_spu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_spu_defs_asm.h ../../inst/io_proc/rtl/iop_spu.r
- *      id: $Id: iop_spu_defs_asm.h,v 1.5 2005/04/24 18:31:06 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_spu_rw_r 4
-/* Register rw_r, scope iop_spu, type rw */
-#define reg_iop_spu_rw_r_offset 0
-
-/* Register rw_seq_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_seq_pc___addr___lsb 0
-#define reg_iop_spu_rw_seq_pc___addr___width 12
-#define reg_iop_spu_rw_seq_pc_offset 64
-
-/* Register rw_fsm_pc, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_pc___addr___lsb 0
-#define reg_iop_spu_rw_fsm_pc___addr___width 12
-#define reg_iop_spu_rw_fsm_pc_offset 68
-
-/* Register rw_ctrl, scope iop_spu, type rw */
-#define reg_iop_spu_rw_ctrl___fsm___lsb 0
-#define reg_iop_spu_rw_ctrl___fsm___width 1
-#define reg_iop_spu_rw_ctrl___fsm___bit 0
-#define reg_iop_spu_rw_ctrl___en___lsb 1
-#define reg_iop_spu_rw_ctrl___en___width 1
-#define reg_iop_spu_rw_ctrl___en___bit 1
-#define reg_iop_spu_rw_ctrl_offset 72
-
-/* Register rw_fsm_inputs3_0, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___lsb 0
-#define reg_iop_spu_rw_fsm_inputs3_0___val0___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___lsb 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src0___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___lsb 8
-#define reg_iop_spu_rw_fsm_inputs3_0___val1___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___lsb 13
-#define reg_iop_spu_rw_fsm_inputs3_0___src1___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___lsb 16
-#define reg_iop_spu_rw_fsm_inputs3_0___val2___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___lsb 21
-#define reg_iop_spu_rw_fsm_inputs3_0___src2___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___lsb 24
-#define reg_iop_spu_rw_fsm_inputs3_0___val3___width 5
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___lsb 29
-#define reg_iop_spu_rw_fsm_inputs3_0___src3___width 3
-#define reg_iop_spu_rw_fsm_inputs3_0_offset 76
-
-/* Register rw_fsm_inputs7_4, scope iop_spu, type rw */
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___lsb 0
-#define reg_iop_spu_rw_fsm_inputs7_4___val4___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___lsb 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src4___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___lsb 8
-#define reg_iop_spu_rw_fsm_inputs7_4___val5___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___lsb 13
-#define reg_iop_spu_rw_fsm_inputs7_4___src5___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___lsb 16
-#define reg_iop_spu_rw_fsm_inputs7_4___val6___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___lsb 21
-#define reg_iop_spu_rw_fsm_inputs7_4___src6___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___lsb 24
-#define reg_iop_spu_rw_fsm_inputs7_4___val7___width 5
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___lsb 29
-#define reg_iop_spu_rw_fsm_inputs7_4___src7___width 3
-#define reg_iop_spu_rw_fsm_inputs7_4_offset 80
-
-/* Register rw_gio_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_offset 84
-
-/* Register rw_bus0_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus0_out_offset 88
-
-/* Register rw_bus1_out, scope iop_spu, type rw */
-#define reg_iop_spu_rw_bus1_out_offset 92
-
-/* Register r_gio_in, scope iop_spu, type r */
-#define reg_iop_spu_r_gio_in_offset 96
-
-/* Register r_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus0_in_offset 100
-
-/* Register r_bus1_in, scope iop_spu, type r */
-#define reg_iop_spu_r_bus1_in_offset 104
-
-/* Register rw_gio_out_set, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_set_offset 108
-
-/* Register rw_gio_out_clr, scope iop_spu, type rw */
-#define reg_iop_spu_rw_gio_out_clr_offset 112
-
-/* Register rs_wr_stat, scope iop_spu, type rs */
-#define reg_iop_spu_rs_wr_stat___r0___lsb 0
-#define reg_iop_spu_rs_wr_stat___r0___width 1
-#define reg_iop_spu_rs_wr_stat___r0___bit 0
-#define reg_iop_spu_rs_wr_stat___r1___lsb 1
-#define reg_iop_spu_rs_wr_stat___r1___width 1
-#define reg_iop_spu_rs_wr_stat___r1___bit 1
-#define reg_iop_spu_rs_wr_stat___r2___lsb 2
-#define reg_iop_spu_rs_wr_stat___r2___width 1
-#define reg_iop_spu_rs_wr_stat___r2___bit 2
-#define reg_iop_spu_rs_wr_stat___r3___lsb 3
-#define reg_iop_spu_rs_wr_stat___r3___width 1
-#define reg_iop_spu_rs_wr_stat___r3___bit 3
-#define reg_iop_spu_rs_wr_stat___r4___lsb 4
-#define reg_iop_spu_rs_wr_stat___r4___width 1
-#define reg_iop_spu_rs_wr_stat___r4___bit 4
-#define reg_iop_spu_rs_wr_stat___r5___lsb 5
-#define reg_iop_spu_rs_wr_stat___r5___width 1
-#define reg_iop_spu_rs_wr_stat___r5___bit 5
-#define reg_iop_spu_rs_wr_stat___r6___lsb 6
-#define reg_iop_spu_rs_wr_stat___r6___width 1
-#define reg_iop_spu_rs_wr_stat___r6___bit 6
-#define reg_iop_spu_rs_wr_stat___r7___lsb 7
-#define reg_iop_spu_rs_wr_stat___r7___width 1
-#define reg_iop_spu_rs_wr_stat___r7___bit 7
-#define reg_iop_spu_rs_wr_stat___r8___lsb 8
-#define reg_iop_spu_rs_wr_stat___r8___width 1
-#define reg_iop_spu_rs_wr_stat___r8___bit 8
-#define reg_iop_spu_rs_wr_stat___r9___lsb 9
-#define reg_iop_spu_rs_wr_stat___r9___width 1
-#define reg_iop_spu_rs_wr_stat___r9___bit 9
-#define reg_iop_spu_rs_wr_stat___r10___lsb 10
-#define reg_iop_spu_rs_wr_stat___r10___width 1
-#define reg_iop_spu_rs_wr_stat___r10___bit 10
-#define reg_iop_spu_rs_wr_stat___r11___lsb 11
-#define reg_iop_spu_rs_wr_stat___r11___width 1
-#define reg_iop_spu_rs_wr_stat___r11___bit 11
-#define reg_iop_spu_rs_wr_stat___r12___lsb 12
-#define reg_iop_spu_rs_wr_stat___r12___width 1
-#define reg_iop_spu_rs_wr_stat___r12___bit 12
-#define reg_iop_spu_rs_wr_stat___r13___lsb 13
-#define reg_iop_spu_rs_wr_stat___r13___width 1
-#define reg_iop_spu_rs_wr_stat___r13___bit 13
-#define reg_iop_spu_rs_wr_stat___r14___lsb 14
-#define reg_iop_spu_rs_wr_stat___r14___width 1
-#define reg_iop_spu_rs_wr_stat___r14___bit 14
-#define reg_iop_spu_rs_wr_stat___r15___lsb 15
-#define reg_iop_spu_rs_wr_stat___r15___width 1
-#define reg_iop_spu_rs_wr_stat___r15___bit 15
-#define reg_iop_spu_rs_wr_stat_offset 116
-
-/* Register r_wr_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_wr_stat___r0___lsb 0
-#define reg_iop_spu_r_wr_stat___r0___width 1
-#define reg_iop_spu_r_wr_stat___r0___bit 0
-#define reg_iop_spu_r_wr_stat___r1___lsb 1
-#define reg_iop_spu_r_wr_stat___r1___width 1
-#define reg_iop_spu_r_wr_stat___r1___bit 1
-#define reg_iop_spu_r_wr_stat___r2___lsb 2
-#define reg_iop_spu_r_wr_stat___r2___width 1
-#define reg_iop_spu_r_wr_stat___r2___bit 2
-#define reg_iop_spu_r_wr_stat___r3___lsb 3
-#define reg_iop_spu_r_wr_stat___r3___width 1
-#define reg_iop_spu_r_wr_stat___r3___bit 3
-#define reg_iop_spu_r_wr_stat___r4___lsb 4
-#define reg_iop_spu_r_wr_stat___r4___width 1
-#define reg_iop_spu_r_wr_stat___r4___bit 4
-#define reg_iop_spu_r_wr_stat___r5___lsb 5
-#define reg_iop_spu_r_wr_stat___r5___width 1
-#define reg_iop_spu_r_wr_stat___r5___bit 5
-#define reg_iop_spu_r_wr_stat___r6___lsb 6
-#define reg_iop_spu_r_wr_stat___r6___width 1
-#define reg_iop_spu_r_wr_stat___r6___bit 6
-#define reg_iop_spu_r_wr_stat___r7___lsb 7
-#define reg_iop_spu_r_wr_stat___r7___width 1
-#define reg_iop_spu_r_wr_stat___r7___bit 7
-#define reg_iop_spu_r_wr_stat___r8___lsb 8
-#define reg_iop_spu_r_wr_stat___r8___width 1
-#define reg_iop_spu_r_wr_stat___r8___bit 8
-#define reg_iop_spu_r_wr_stat___r9___lsb 9
-#define reg_iop_spu_r_wr_stat___r9___width 1
-#define reg_iop_spu_r_wr_stat___r9___bit 9
-#define reg_iop_spu_r_wr_stat___r10___lsb 10
-#define reg_iop_spu_r_wr_stat___r10___width 1
-#define reg_iop_spu_r_wr_stat___r10___bit 10
-#define reg_iop_spu_r_wr_stat___r11___lsb 11
-#define reg_iop_spu_r_wr_stat___r11___width 1
-#define reg_iop_spu_r_wr_stat___r11___bit 11
-#define reg_iop_spu_r_wr_stat___r12___lsb 12
-#define reg_iop_spu_r_wr_stat___r12___width 1
-#define reg_iop_spu_r_wr_stat___r12___bit 12
-#define reg_iop_spu_r_wr_stat___r13___lsb 13
-#define reg_iop_spu_r_wr_stat___r13___width 1
-#define reg_iop_spu_r_wr_stat___r13___bit 13
-#define reg_iop_spu_r_wr_stat___r14___lsb 14
-#define reg_iop_spu_r_wr_stat___r14___width 1
-#define reg_iop_spu_r_wr_stat___r14___bit 14
-#define reg_iop_spu_r_wr_stat___r15___lsb 15
-#define reg_iop_spu_r_wr_stat___r15___width 1
-#define reg_iop_spu_r_wr_stat___r15___bit 15
-#define reg_iop_spu_r_wr_stat_offset 120
-
-/* Register r_reg_indexed_by_bus0_in, scope iop_spu, type r */
-#define reg_iop_spu_r_reg_indexed_by_bus0_in_offset 124
-
-/* Register r_stat_in, scope iop_spu, type r */
-#define reg_iop_spu_r_stat_in___timer_grp_lo___lsb 0
-#define reg_iop_spu_r_stat_in___timer_grp_lo___width 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___lsb 4
-#define reg_iop_spu_r_stat_in___fifo_out_last___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_last___bit 4
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___lsb 5
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_rdy___bit 5
-#define reg_iop_spu_r_stat_in___fifo_out_all___lsb 6
-#define reg_iop_spu_r_stat_in___fifo_out_all___width 1
-#define reg_iop_spu_r_stat_in___fifo_out_all___bit 6
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___lsb 7
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___width 1
-#define reg_iop_spu_r_stat_in___fifo_in_rdy___bit 7
-#define reg_iop_spu_r_stat_in___dmc_out_all___lsb 8
-#define reg_iop_spu_r_stat_in___dmc_out_all___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_all___bit 8
-#define reg_iop_spu_r_stat_in___dmc_out_dth___lsb 9
-#define reg_iop_spu_r_stat_in___dmc_out_dth___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dth___bit 9
-#define reg_iop_spu_r_stat_in___dmc_out_eop___lsb 10
-#define reg_iop_spu_r_stat_in___dmc_out_eop___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_eop___bit 10
-#define reg_iop_spu_r_stat_in___dmc_out_dv___lsb 11
-#define reg_iop_spu_r_stat_in___dmc_out_dv___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_dv___bit 11
-#define reg_iop_spu_r_stat_in___dmc_out_last___lsb 12
-#define reg_iop_spu_r_stat_in___dmc_out_last___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_last___bit 12
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___lsb 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rq___bit 13
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___lsb 14
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_out_cmd_rdy___bit 14
-#define reg_iop_spu_r_stat_in___pcrc_correct___lsb 15
-#define reg_iop_spu_r_stat_in___pcrc_correct___width 1
-#define reg_iop_spu_r_stat_in___pcrc_correct___bit 15
-#define reg_iop_spu_r_stat_in___timer_grp_hi___lsb 16
-#define reg_iop_spu_r_stat_in___timer_grp_hi___width 4
-#define reg_iop_spu_r_stat_in___dmc_in_sth___lsb 20
-#define reg_iop_spu_r_stat_in___dmc_in_sth___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_sth___bit 20
-#define reg_iop_spu_r_stat_in___dmc_in_full___lsb 21
-#define reg_iop_spu_r_stat_in___dmc_in_full___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_full___bit 21
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___lsb 22
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___width 1
-#define reg_iop_spu_r_stat_in___dmc_in_cmd_rdy___bit 22
-#define reg_iop_spu_r_stat_in___spu_gio_out___lsb 23
-#define reg_iop_spu_r_stat_in___spu_gio_out___width 4
-#define reg_iop_spu_r_stat_in___sync_clk12___lsb 27
-#define reg_iop_spu_r_stat_in___sync_clk12___width 1
-#define reg_iop_spu_r_stat_in___sync_clk12___bit 27
-#define reg_iop_spu_r_stat_in___scrc_out_data___lsb 28
-#define reg_iop_spu_r_stat_in___scrc_out_data___width 1
-#define reg_iop_spu_r_stat_in___scrc_out_data___bit 28
-#define reg_iop_spu_r_stat_in___scrc_in_err___lsb 29
-#define reg_iop_spu_r_stat_in___scrc_in_err___width 1
-#define reg_iop_spu_r_stat_in___scrc_in_err___bit 29
-#define reg_iop_spu_r_stat_in___mc_busy___lsb 30
-#define reg_iop_spu_r_stat_in___mc_busy___width 1
-#define reg_iop_spu_r_stat_in___mc_busy___bit 30
-#define reg_iop_spu_r_stat_in___mc_owned___lsb 31
-#define reg_iop_spu_r_stat_in___mc_owned___width 1
-#define reg_iop_spu_r_stat_in___mc_owned___bit 31
-#define reg_iop_spu_r_stat_in_offset 128
-
-/* Register r_trigger_in, scope iop_spu, type r */
-#define reg_iop_spu_r_trigger_in_offset 132
-
-/* Register r_special_stat, scope iop_spu, type r */
-#define reg_iop_spu_r_special_stat___c_flag___lsb 0
-#define reg_iop_spu_r_special_stat___c_flag___width 1
-#define reg_iop_spu_r_special_stat___c_flag___bit 0
-#define reg_iop_spu_r_special_stat___v_flag___lsb 1
-#define reg_iop_spu_r_special_stat___v_flag___width 1
-#define reg_iop_spu_r_special_stat___v_flag___bit 1
-#define reg_iop_spu_r_special_stat___z_flag___lsb 2
-#define reg_iop_spu_r_special_stat___z_flag___width 1
-#define reg_iop_spu_r_special_stat___z_flag___bit 2
-#define reg_iop_spu_r_special_stat___n_flag___lsb 3
-#define reg_iop_spu_r_special_stat___n_flag___width 1
-#define reg_iop_spu_r_special_stat___n_flag___bit 3
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___lsb 4
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0_r2_0___bit 4
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___lsb 5
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1_r3_0___bit 5
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___lsb 6
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus0m_r2_0___bit 6
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___lsb 7
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___width 1
-#define reg_iop_spu_r_special_stat___xor_bus1m_r3_0___bit 7
-#define reg_iop_spu_r_special_stat___fsm_in0___lsb 8
-#define reg_iop_spu_r_special_stat___fsm_in0___width 1
-#define reg_iop_spu_r_special_stat___fsm_in0___bit 8
-#define reg_iop_spu_r_special_stat___fsm_in1___lsb 9
-#define reg_iop_spu_r_special_stat___fsm_in1___width 1
-#define reg_iop_spu_r_special_stat___fsm_in1___bit 9
-#define reg_iop_spu_r_special_stat___fsm_in2___lsb 10
-#define reg_iop_spu_r_special_stat___fsm_in2___width 1
-#define reg_iop_spu_r_special_stat___fsm_in2___bit 10
-#define reg_iop_spu_r_special_stat___fsm_in3___lsb 11
-#define reg_iop_spu_r_special_stat___fsm_in3___width 1
-#define reg_iop_spu_r_special_stat___fsm_in3___bit 11
-#define reg_iop_spu_r_special_stat___fsm_in4___lsb 12
-#define reg_iop_spu_r_special_stat___fsm_in4___width 1
-#define reg_iop_spu_r_special_stat___fsm_in4___bit 12
-#define reg_iop_spu_r_special_stat___fsm_in5___lsb 13
-#define reg_iop_spu_r_special_stat___fsm_in5___width 1
-#define reg_iop_spu_r_special_stat___fsm_in5___bit 13
-#define reg_iop_spu_r_special_stat___fsm_in6___lsb 14
-#define reg_iop_spu_r_special_stat___fsm_in6___width 1
-#define reg_iop_spu_r_special_stat___fsm_in6___bit 14
-#define reg_iop_spu_r_special_stat___fsm_in7___lsb 15
-#define reg_iop_spu_r_special_stat___fsm_in7___width 1
-#define reg_iop_spu_r_special_stat___fsm_in7___bit 15
-#define reg_iop_spu_r_special_stat___event0___lsb 16
-#define reg_iop_spu_r_special_stat___event0___width 1
-#define reg_iop_spu_r_special_stat___event0___bit 16
-#define reg_iop_spu_r_special_stat___event1___lsb 17
-#define reg_iop_spu_r_special_stat___event1___width 1
-#define reg_iop_spu_r_special_stat___event1___bit 17
-#define reg_iop_spu_r_special_stat___event2___lsb 18
-#define reg_iop_spu_r_special_stat___event2___width 1
-#define reg_iop_spu_r_special_stat___event2___bit 18
-#define reg_iop_spu_r_special_stat___event3___lsb 19
-#define reg_iop_spu_r_special_stat___event3___width 1
-#define reg_iop_spu_r_special_stat___event3___bit 19
-#define reg_iop_spu_r_special_stat_offset 136
-
-/* Register rw_reg_access, scope iop_spu, type rw */
-#define reg_iop_spu_rw_reg_access___addr___lsb 0
-#define reg_iop_spu_rw_reg_access___addr___width 13
-#define reg_iop_spu_rw_reg_access___imm_hi___lsb 16
-#define reg_iop_spu_rw_reg_access___imm_hi___width 16
-#define reg_iop_spu_rw_reg_access_offset 140
-
-#define STRIDE_iop_spu_rw_event_cfg 4
-/* Register rw_event_cfg, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_cfg___addr___lsb 0
-#define reg_iop_spu_rw_event_cfg___addr___width 12
-#define reg_iop_spu_rw_event_cfg___src___lsb 12
-#define reg_iop_spu_rw_event_cfg___src___width 2
-#define reg_iop_spu_rw_event_cfg___eq_en___lsb 14
-#define reg_iop_spu_rw_event_cfg___eq_en___width 1
-#define reg_iop_spu_rw_event_cfg___eq_en___bit 14
-#define reg_iop_spu_rw_event_cfg___eq_inv___lsb 15
-#define reg_iop_spu_rw_event_cfg___eq_inv___width 1
-#define reg_iop_spu_rw_event_cfg___eq_inv___bit 15
-#define reg_iop_spu_rw_event_cfg___gt_en___lsb 16
-#define reg_iop_spu_rw_event_cfg___gt_en___width 1
-#define reg_iop_spu_rw_event_cfg___gt_en___bit 16
-#define reg_iop_spu_rw_event_cfg___gt_inv___lsb 17
-#define reg_iop_spu_rw_event_cfg___gt_inv___width 1
-#define reg_iop_spu_rw_event_cfg___gt_inv___bit 17
-#define reg_iop_spu_rw_event_cfg_offset 144
-
-#define STRIDE_iop_spu_rw_event_mask 4
-/* Register rw_event_mask, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_mask_offset 160
-
-#define STRIDE_iop_spu_rw_event_val 4
-/* Register rw_event_val, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_val_offset 176
-
-/* Register rw_event_ret, scope iop_spu, type rw */
-#define reg_iop_spu_rw_event_ret___addr___lsb 0
-#define reg_iop_spu_rw_event_ret___addr___width 12
-#define reg_iop_spu_rw_event_ret_offset 192
-
-/* Register r_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_trace___fsm___lsb 0
-#define reg_iop_spu_r_trace___fsm___width 1
-#define reg_iop_spu_r_trace___fsm___bit 0
-#define reg_iop_spu_r_trace___en___lsb 1
-#define reg_iop_spu_r_trace___en___width 1
-#define reg_iop_spu_r_trace___en___bit 1
-#define reg_iop_spu_r_trace___c_flag___lsb 2
-#define reg_iop_spu_r_trace___c_flag___width 1
-#define reg_iop_spu_r_trace___c_flag___bit 2
-#define reg_iop_spu_r_trace___v_flag___lsb 3
-#define reg_iop_spu_r_trace___v_flag___width 1
-#define reg_iop_spu_r_trace___v_flag___bit 3
-#define reg_iop_spu_r_trace___z_flag___lsb 4
-#define reg_iop_spu_r_trace___z_flag___width 1
-#define reg_iop_spu_r_trace___z_flag___bit 4
-#define reg_iop_spu_r_trace___n_flag___lsb 5
-#define reg_iop_spu_r_trace___n_flag___width 1
-#define reg_iop_spu_r_trace___n_flag___bit 5
-#define reg_iop_spu_r_trace___seq_addr___lsb 6
-#define reg_iop_spu_r_trace___seq_addr___width 12
-#define reg_iop_spu_r_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_trace___fsm_addr___width 12
-#define reg_iop_spu_r_trace_offset 196
-
-/* Register r_fsm_trace, scope iop_spu, type r */
-#define reg_iop_spu_r_fsm_trace___fsm___lsb 0
-#define reg_iop_spu_r_fsm_trace___fsm___width 1
-#define reg_iop_spu_r_fsm_trace___fsm___bit 0
-#define reg_iop_spu_r_fsm_trace___en___lsb 1
-#define reg_iop_spu_r_fsm_trace___en___width 1
-#define reg_iop_spu_r_fsm_trace___en___bit 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___lsb 2
-#define reg_iop_spu_r_fsm_trace___tmr_done___width 1
-#define reg_iop_spu_r_fsm_trace___tmr_done___bit 2
-#define reg_iop_spu_r_fsm_trace___inp0___lsb 3
-#define reg_iop_spu_r_fsm_trace___inp0___width 1
-#define reg_iop_spu_r_fsm_trace___inp0___bit 3
-#define reg_iop_spu_r_fsm_trace___inp1___lsb 4
-#define reg_iop_spu_r_fsm_trace___inp1___width 1
-#define reg_iop_spu_r_fsm_trace___inp1___bit 4
-#define reg_iop_spu_r_fsm_trace___inp2___lsb 5
-#define reg_iop_spu_r_fsm_trace___inp2___width 1
-#define reg_iop_spu_r_fsm_trace___inp2___bit 5
-#define reg_iop_spu_r_fsm_trace___inp3___lsb 6
-#define reg_iop_spu_r_fsm_trace___inp3___width 1
-#define reg_iop_spu_r_fsm_trace___inp3___bit 6
-#define reg_iop_spu_r_fsm_trace___event0___lsb 7
-#define reg_iop_spu_r_fsm_trace___event0___width 1
-#define reg_iop_spu_r_fsm_trace___event0___bit 7
-#define reg_iop_spu_r_fsm_trace___event1___lsb 8
-#define reg_iop_spu_r_fsm_trace___event1___width 1
-#define reg_iop_spu_r_fsm_trace___event1___bit 8
-#define reg_iop_spu_r_fsm_trace___event2___lsb 9
-#define reg_iop_spu_r_fsm_trace___event2___width 1
-#define reg_iop_spu_r_fsm_trace___event2___bit 9
-#define reg_iop_spu_r_fsm_trace___event3___lsb 10
-#define reg_iop_spu_r_fsm_trace___event3___width 1
-#define reg_iop_spu_r_fsm_trace___event3___bit 10
-#define reg_iop_spu_r_fsm_trace___gio_out___lsb 11
-#define reg_iop_spu_r_fsm_trace___gio_out___width 8
-#define reg_iop_spu_r_fsm_trace___fsm_addr___lsb 20
-#define reg_iop_spu_r_fsm_trace___fsm_addr___width 12
-#define reg_iop_spu_r_fsm_trace_offset 200
-
-#define STRIDE_iop_spu_rw_brp 4
-/* Register rw_brp, scope iop_spu, type rw */
-#define reg_iop_spu_rw_brp___addr___lsb 0
-#define reg_iop_spu_rw_brp___addr___width 12
-#define reg_iop_spu_rw_brp___fsm___lsb 12
-#define reg_iop_spu_rw_brp___fsm___width 1
-#define reg_iop_spu_rw_brp___fsm___bit 12
-#define reg_iop_spu_rw_brp___en___lsb 13
-#define reg_iop_spu_rw_brp___en___width 1
-#define reg_iop_spu_rw_brp___en___bit 13
-#define reg_iop_spu_rw_brp_offset 204
-
-
-/* Constants */
-#define regk_iop_spu_attn_hi                      0x00000005
-#define regk_iop_spu_attn_lo                      0x00000005
-#define regk_iop_spu_attn_r0                      0x00000000
-#define regk_iop_spu_attn_r1                      0x00000001
-#define regk_iop_spu_attn_r10                     0x00000002
-#define regk_iop_spu_attn_r11                     0x00000003
-#define regk_iop_spu_attn_r12                     0x00000004
-#define regk_iop_spu_attn_r13                     0x00000005
-#define regk_iop_spu_attn_r14                     0x00000006
-#define regk_iop_spu_attn_r15                     0x00000007
-#define regk_iop_spu_attn_r2                      0x00000002
-#define regk_iop_spu_attn_r3                      0x00000003
-#define regk_iop_spu_attn_r4                      0x00000004
-#define regk_iop_spu_attn_r5                      0x00000005
-#define regk_iop_spu_attn_r6                      0x00000006
-#define regk_iop_spu_attn_r7                      0x00000007
-#define regk_iop_spu_attn_r8                      0x00000000
-#define regk_iop_spu_attn_r9                      0x00000001
-#define regk_iop_spu_c                            0x00000000
-#define regk_iop_spu_flag                         0x00000002
-#define regk_iop_spu_gio_in                       0x00000000
-#define regk_iop_spu_gio_out                      0x00000005
-#define regk_iop_spu_gio_out0                     0x00000008
-#define regk_iop_spu_gio_out1                     0x00000009
-#define regk_iop_spu_gio_out2                     0x0000000a
-#define regk_iop_spu_gio_out3                     0x0000000b
-#define regk_iop_spu_gio_out4                     0x0000000c
-#define regk_iop_spu_gio_out5                     0x0000000d
-#define regk_iop_spu_gio_out6                     0x0000000e
-#define regk_iop_spu_gio_out7                     0x0000000f
-#define regk_iop_spu_n                            0x00000003
-#define regk_iop_spu_no                           0x00000000
-#define regk_iop_spu_r0                           0x00000008
-#define regk_iop_spu_r1                           0x00000009
-#define regk_iop_spu_r10                          0x0000000a
-#define regk_iop_spu_r11                          0x0000000b
-#define regk_iop_spu_r12                          0x0000000c
-#define regk_iop_spu_r13                          0x0000000d
-#define regk_iop_spu_r14                          0x0000000e
-#define regk_iop_spu_r15                          0x0000000f
-#define regk_iop_spu_r2                           0x0000000a
-#define regk_iop_spu_r3                           0x0000000b
-#define regk_iop_spu_r4                           0x0000000c
-#define regk_iop_spu_r5                           0x0000000d
-#define regk_iop_spu_r6                           0x0000000e
-#define regk_iop_spu_r7                           0x0000000f
-#define regk_iop_spu_r8                           0x00000008
-#define regk_iop_spu_r9                           0x00000009
-#define regk_iop_spu_reg_hi                       0x00000002
-#define regk_iop_spu_reg_lo                       0x00000002
-#define regk_iop_spu_rw_brp_default               0x00000000
-#define regk_iop_spu_rw_brp_size                  0x00000004
-#define regk_iop_spu_rw_ctrl_default              0x00000000
-#define regk_iop_spu_rw_event_cfg_size            0x00000004
-#define regk_iop_spu_rw_event_mask_size           0x00000004
-#define regk_iop_spu_rw_event_val_size            0x00000004
-#define regk_iop_spu_rw_gio_out_default           0x00000000
-#define regk_iop_spu_rw_r_size                    0x00000010
-#define regk_iop_spu_rw_reg_access_default        0x00000000
-#define regk_iop_spu_stat_in                      0x00000002
-#define regk_iop_spu_statin_hi                    0x00000004
-#define regk_iop_spu_statin_lo                    0x00000004
-#define regk_iop_spu_trig                         0x00000003
-#define regk_iop_spu_trigger                      0x00000006
-#define regk_iop_spu_v                            0x00000001
-#define regk_iop_spu_wsts_gioout_spec             0x00000001
-#define regk_iop_spu_xor                          0x00000003
-#define regk_iop_spu_xor_bus0_r2_0                0x00000000
-#define regk_iop_spu_xor_bus0m_r2_0               0x00000002
-#define regk_iop_spu_xor_bus1_r3_0                0x00000001
-#define regk_iop_spu_xor_bus1m_r3_0               0x00000003
-#define regk_iop_spu_yes                          0x00000001
-#define regk_iop_spu_z                            0x00000002
-#endif /* __iop_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
deleted file mode 100644
index 4f4c7340d39a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cfg_defs_asm.h
+++ /dev/null
@@ -1,1053 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cfg_defs_asm_h
-#define __iop_sw_cfg_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cfg_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cfg.r
- *      id: $Id: iop_sw_cfg_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_crc_par0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par0_owner_offset 0
-
-/* Register rw_crc_par1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_crc_par1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_crc_par1_owner_offset 4
-
-/* Register rw_dmc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in0_owner_offset 8
-
-/* Register rw_dmc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_in1_owner_offset 12
-
-/* Register rw_dmc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out0_owner_offset 16
-
-/* Register rw_dmc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_dmc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_dmc_out1_owner_offset 20
-
-/* Register rw_fifo_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_owner_offset 24
-
-/* Register rw_fifo_in0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in0_extra_owner_offset 28
-
-/* Register rw_fifo_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_owner_offset 32
-
-/* Register rw_fifo_in1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_in1_extra_owner_offset 36
-
-/* Register rw_fifo_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_owner_offset 40
-
-/* Register rw_fifo_out0_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out0_extra_owner_offset 44
-
-/* Register rw_fifo_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_owner_offset 48
-
-/* Register rw_fifo_out1_extra_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_fifo_out1_extra_owner_offset 52
-
-/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_in_owner_offset 56
-
-/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_sap_out_owner_offset 60
-
-/* Register rw_scrc_in0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in0_owner_offset 64
-
-/* Register rw_scrc_in1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_in1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_in1_owner_offset 68
-
-/* Register rw_scrc_out0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out0_owner_offset 72
-
-/* Register rw_scrc_out1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_scrc_out1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_scrc_out1_owner_offset 76
-
-/* Register rw_spu0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu0_owner_offset 80
-
-/* Register rw_spu1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_spu1_owner_offset 84
-
-/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 88
-
-/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 92
-
-/* Register rw_timer_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp2_owner_offset 96
-
-/* Register rw_timer_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_timer_grp3_owner_offset 100
-
-/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 104
-
-/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 108
-
-/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 112
-
-/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 116
-
-/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 120
-
-/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 124
-
-/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 128
-
-/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2
-#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 132
-
-/* Register rw_bus0_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus0_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus0_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus0_mask_offset 136
-
-/* Register rw_bus0_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus0_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus0_oe_mask_offset 140
-
-/* Register rw_bus1_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_mask___byte0___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___lsb 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte1___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___lsb 16
-#define reg_iop_sw_cfg_rw_bus1_mask___byte2___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___lsb 24
-#define reg_iop_sw_cfg_rw_bus1_mask___byte3___width 8
-#define reg_iop_sw_cfg_rw_bus1_mask_offset 144
-
-/* Register rw_bus1_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___lsb 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte0___bit 0
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___lsb 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte1___bit 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___lsb 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte2___bit 2
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___lsb 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___width 1
-#define reg_iop_sw_cfg_rw_bus1_oe_mask___byte3___bit 3
-#define reg_iop_sw_cfg_rw_bus1_oe_mask_offset 148
-
-/* Register rw_gio_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_mask_offset 152
-
-/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0
-#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32
-#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 156
-
-/* Register rw_pinmapping, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___lsb 0
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___lsb 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___lsb 4
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___lsb 6
-#define reg_iop_sw_cfg_rw_pinmapping___bus0_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___lsb 8
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___lsb 10
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte1___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___lsb 12
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte2___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___lsb 14
-#define reg_iop_sw_cfg_rw_pinmapping___bus1_byte3___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 16
-#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 18
-#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 20
-#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 22
-#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 24
-#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 26
-#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 28
-#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 30
-#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2
-#define reg_iop_sw_cfg_rw_pinmapping_offset 160
-
-/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___lsb 0
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___lsb 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___lsb 6
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___lsb 9
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus0_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___lsb 12
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___lsb 15
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___lsb 18
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_lo_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___lsb 21
-#define reg_iop_sw_cfg_rw_bus_out_cfg___bus1_hi_oe___width 3
-#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 164
-
-/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 168
-
-/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 172
-
-/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 176
-
-/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 180
-
-/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 184
-
-/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 188
-
-/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 192
-
-/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 6
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 10
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 12
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 16
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 18
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 4
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 22
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 2
-#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 196
-
-/* Register rw_spu0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu0_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu0_cfg_offset 200
-
-/* Register rw_spu1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___lsb 0
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus0_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___lsb 2
-#define reg_iop_sw_cfg_rw_spu1_cfg___bus1_in___width 2
-#define reg_iop_sw_cfg_rw_spu1_cfg_offset 204
-
-/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 208
-
-/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 212
-
-/* Register rw_timer_grp2_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp2_cfg_offset 216
-
-/* Register rw_timer_grp3_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___lsb 0
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___ext_clk___width 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___lsb 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_en___bit 3
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___lsb 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_en___bit 4
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___lsb 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_en___bit 5
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___lsb 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_en___bit 6
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___lsb 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr0_dis___bit 7
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___lsb 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr1_dis___bit 8
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___lsb 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr2_dis___bit 9
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___lsb 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___width 1
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg___tmr3_dis___bit 10
-#define reg_iop_sw_cfg_rw_timer_grp3_cfg_offset 220
-
-/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15
-#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 224
-
-/* Register rw_pdp0_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___dmc0_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp0_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp0_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp0_cfg_offset 228
-
-/* Register rw_pdp1_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___lsb 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___dmc1_usr___bit 0
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___lsb 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_strb___width 5
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___lsb 6
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_src___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___lsb 9
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_size___width 3
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___lsb 12
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_last___width 2
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___lsb 14
-#define reg_iop_sw_cfg_rw_pdp1_cfg___in_strb___width 4
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___lsb 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___width 1
-#define reg_iop_sw_cfg_rw_pdp1_cfg___out_src___bit 18
-#define reg_iop_sw_cfg_rw_pdp1_cfg_offset 232
-
-/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___lsb 0
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___lsb 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___lsb 6
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___lsb 9
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___lsb 11
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in0_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___lsb 14
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_data___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___lsb 17
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_last___width 2
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___lsb 19
-#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in1_strb___width 3
-#define reg_iop_sw_cfg_rw_sdp_cfg_offset 236
-
-
-/* Constants */
-#define regk_iop_sw_cfg_a                         0x00000001
-#define regk_iop_sw_cfg_b                         0x00000002
-#define regk_iop_sw_cfg_bus0                      0x00000000
-#define regk_iop_sw_cfg_bus0_rot16                0x00000004
-#define regk_iop_sw_cfg_bus0_rot24                0x00000006
-#define regk_iop_sw_cfg_bus0_rot8                 0x00000002
-#define regk_iop_sw_cfg_bus1                      0x00000001
-#define regk_iop_sw_cfg_bus1_rot16                0x00000005
-#define regk_iop_sw_cfg_bus1_rot24                0x00000007
-#define regk_iop_sw_cfg_bus1_rot8                 0x00000003
-#define regk_iop_sw_cfg_clk12                     0x00000000
-#define regk_iop_sw_cfg_cpu                       0x00000000
-#define regk_iop_sw_cfg_dmc0                      0x00000000
-#define regk_iop_sw_cfg_dmc1                      0x00000001
-#define regk_iop_sw_cfg_gated_clk0                0x00000010
-#define regk_iop_sw_cfg_gated_clk1                0x00000011
-#define regk_iop_sw_cfg_gated_clk2                0x00000012
-#define regk_iop_sw_cfg_gated_clk3                0x00000013
-#define regk_iop_sw_cfg_gio0                      0x00000004
-#define regk_iop_sw_cfg_gio1                      0x00000001
-#define regk_iop_sw_cfg_gio2                      0x00000005
-#define regk_iop_sw_cfg_gio3                      0x00000002
-#define regk_iop_sw_cfg_gio4                      0x00000006
-#define regk_iop_sw_cfg_gio5                      0x00000003
-#define regk_iop_sw_cfg_gio6                      0x00000007
-#define regk_iop_sw_cfg_gio7                      0x00000004
-#define regk_iop_sw_cfg_gio_in0                   0x00000000
-#define regk_iop_sw_cfg_gio_in1                   0x00000001
-#define regk_iop_sw_cfg_gio_in10                  0x00000002
-#define regk_iop_sw_cfg_gio_in11                  0x00000003
-#define regk_iop_sw_cfg_gio_in14                  0x00000004
-#define regk_iop_sw_cfg_gio_in15                  0x00000005
-#define regk_iop_sw_cfg_gio_in18                  0x00000002
-#define regk_iop_sw_cfg_gio_in19                  0x00000003
-#define regk_iop_sw_cfg_gio_in20                  0x00000004
-#define regk_iop_sw_cfg_gio_in21                  0x00000005
-#define regk_iop_sw_cfg_gio_in26                  0x00000006
-#define regk_iop_sw_cfg_gio_in27                  0x00000007
-#define regk_iop_sw_cfg_gio_in28                  0x00000006
-#define regk_iop_sw_cfg_gio_in29                  0x00000007
-#define regk_iop_sw_cfg_gio_in4                   0x00000000
-#define regk_iop_sw_cfg_gio_in5                   0x00000001
-#define regk_iop_sw_cfg_last_timer_grp0_tmr2      0x00000001
-#define regk_iop_sw_cfg_last_timer_grp1_tmr2      0x00000001
-#define regk_iop_sw_cfg_last_timer_grp2_tmr2      0x00000002
-#define regk_iop_sw_cfg_last_timer_grp2_tmr3      0x00000003
-#define regk_iop_sw_cfg_last_timer_grp3_tmr2      0x00000002
-#define regk_iop_sw_cfg_last_timer_grp3_tmr3      0x00000003
-#define regk_iop_sw_cfg_mpu                       0x00000001
-#define regk_iop_sw_cfg_none                      0x00000000
-#define regk_iop_sw_cfg_par0                      0x00000000
-#define regk_iop_sw_cfg_par1                      0x00000001
-#define regk_iop_sw_cfg_pdp_out0                  0x00000002
-#define regk_iop_sw_cfg_pdp_out0_hi               0x00000001
-#define regk_iop_sw_cfg_pdp_out0_hi_rot8          0x00000005
-#define regk_iop_sw_cfg_pdp_out0_lo               0x00000000
-#define regk_iop_sw_cfg_pdp_out0_lo_rot8          0x00000004
-#define regk_iop_sw_cfg_pdp_out1                  0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi               0x00000003
-#define regk_iop_sw_cfg_pdp_out1_hi_rot8          0x00000005
-#define regk_iop_sw_cfg_pdp_out1_lo               0x00000002
-#define regk_iop_sw_cfg_pdp_out1_lo_rot8          0x00000004
-#define regk_iop_sw_cfg_rw_bus0_mask_default      0x00000000
-#define regk_iop_sw_cfg_rw_bus0_oe_mask_default   0x00000000
-#define regk_iop_sw_cfg_rw_bus1_mask_default      0x00000000
-#define regk_iop_sw_cfg_rw_bus1_oe_mask_default   0x00000000
-#define regk_iop_sw_cfg_rw_bus_out_cfg_default    0x00000000
-#define regk_iop_sw_cfg_rw_crc_par0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_crc_par1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_in1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_dmc_out1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_in1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_extra_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_fifo_out1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_mask_default       0x00000000
-#define regk_iop_sw_cfg_rw_gio_oe_mask_default    0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_pdp0_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_pdp1_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_pinmapping_default     0x55555555
-#define regk_iop_sw_cfg_rw_sap_in_owner_default   0x00000000
-#define regk_iop_sw_cfg_rw_sap_out_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_in1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_scrc_out1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_sdp_cfg_default        0x00000000
-#define regk_iop_sw_cfg_rw_spu0_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_spu0_owner_default     0x00000000
-#define regk_iop_sw_cfg_rw_spu1_cfg_default       0x00000000
-#define regk_iop_sw_cfg_rw_spu1_owner_default     0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp2_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_cfg_default  0x00000000
-#define regk_iop_sw_cfg_rw_timer_grp3_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default  0x00000000
-#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default  0x00000000
-#define regk_iop_sw_cfg_sdp_out0                  0x00000008
-#define regk_iop_sw_cfg_sdp_out1                  0x00000009
-#define regk_iop_sw_cfg_size16                    0x00000002
-#define regk_iop_sw_cfg_size24                    0x00000003
-#define regk_iop_sw_cfg_size32                    0x00000004
-#define regk_iop_sw_cfg_size8                     0x00000001
-#define regk_iop_sw_cfg_spu0                      0x00000002
-#define regk_iop_sw_cfg_spu0_bus_out0_hi          0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out0_lo          0x00000006
-#define regk_iop_sw_cfg_spu0_bus_out1_hi          0x00000007
-#define regk_iop_sw_cfg_spu0_bus_out1_lo          0x00000007
-#define regk_iop_sw_cfg_spu0_g0                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g1                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g2                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g3                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g4                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g5                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g6                   0x0000000e
-#define regk_iop_sw_cfg_spu0_g7                   0x0000000e
-#define regk_iop_sw_cfg_spu0_gio0                 0x00000000
-#define regk_iop_sw_cfg_spu0_gio1                 0x00000001
-#define regk_iop_sw_cfg_spu0_gio2                 0x00000000
-#define regk_iop_sw_cfg_spu0_gio5                 0x00000005
-#define regk_iop_sw_cfg_spu0_gio6                 0x00000006
-#define regk_iop_sw_cfg_spu0_gio7                 0x00000007
-#define regk_iop_sw_cfg_spu0_gio_out0             0x00000008
-#define regk_iop_sw_cfg_spu0_gio_out1             0x00000009
-#define regk_iop_sw_cfg_spu0_gio_out2             0x0000000a
-#define regk_iop_sw_cfg_spu0_gio_out3             0x0000000b
-#define regk_iop_sw_cfg_spu0_gio_out4             0x0000000c
-#define regk_iop_sw_cfg_spu0_gio_out5             0x0000000d
-#define regk_iop_sw_cfg_spu0_gio_out6             0x0000000e
-#define regk_iop_sw_cfg_spu0_gio_out7             0x0000000f
-#define regk_iop_sw_cfg_spu0_gioout0              0x00000000
-#define regk_iop_sw_cfg_spu0_gioout1              0x00000000
-#define regk_iop_sw_cfg_spu0_gioout10             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout11             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout12             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout13             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout14             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout15             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout16             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout17             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout18             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout19             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout2              0x00000002
-#define regk_iop_sw_cfg_spu0_gioout20             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout21             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout22             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout23             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout24             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout25             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout26             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout27             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout28             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout29             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout3              0x00000002
-#define regk_iop_sw_cfg_spu0_gioout30             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout31             0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout4              0x00000004
-#define regk_iop_sw_cfg_spu0_gioout5              0x00000004
-#define regk_iop_sw_cfg_spu0_gioout6              0x00000006
-#define regk_iop_sw_cfg_spu0_gioout7              0x00000006
-#define regk_iop_sw_cfg_spu0_gioout8              0x0000000e
-#define regk_iop_sw_cfg_spu0_gioout9              0x0000000e
-#define regk_iop_sw_cfg_spu1                      0x00000003
-#define regk_iop_sw_cfg_spu1_bus_out0_hi          0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out0_lo          0x00000006
-#define regk_iop_sw_cfg_spu1_bus_out1_hi          0x00000007
-#define regk_iop_sw_cfg_spu1_bus_out1_lo          0x00000007
-#define regk_iop_sw_cfg_spu1_g0                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g1                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g2                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g3                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g4                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g5                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g6                   0x0000000f
-#define regk_iop_sw_cfg_spu1_g7                   0x0000000f
-#define regk_iop_sw_cfg_spu1_gio0                 0x00000002
-#define regk_iop_sw_cfg_spu1_gio1                 0x00000003
-#define regk_iop_sw_cfg_spu1_gio2                 0x00000002
-#define regk_iop_sw_cfg_spu1_gio5                 0x00000005
-#define regk_iop_sw_cfg_spu1_gio6                 0x00000006
-#define regk_iop_sw_cfg_spu1_gio7                 0x00000007
-#define regk_iop_sw_cfg_spu1_gio_out0             0x00000008
-#define regk_iop_sw_cfg_spu1_gio_out1             0x00000009
-#define regk_iop_sw_cfg_spu1_gio_out2             0x0000000a
-#define regk_iop_sw_cfg_spu1_gio_out3             0x0000000b
-#define regk_iop_sw_cfg_spu1_gio_out4             0x0000000c
-#define regk_iop_sw_cfg_spu1_gio_out5             0x0000000d
-#define regk_iop_sw_cfg_spu1_gio_out6             0x0000000e
-#define regk_iop_sw_cfg_spu1_gio_out7             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout0              0x00000001
-#define regk_iop_sw_cfg_spu1_gioout1              0x00000001
-#define regk_iop_sw_cfg_spu1_gioout10             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout11             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout12             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout13             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout14             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout15             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout16             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout17             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout18             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout19             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout2              0x00000003
-#define regk_iop_sw_cfg_spu1_gioout20             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout21             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout22             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout23             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout24             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout25             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout26             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout27             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout28             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout29             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout3              0x00000003
-#define regk_iop_sw_cfg_spu1_gioout30             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout31             0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout4              0x00000005
-#define regk_iop_sw_cfg_spu1_gioout5              0x00000005
-#define regk_iop_sw_cfg_spu1_gioout6              0x00000007
-#define regk_iop_sw_cfg_spu1_gioout7              0x00000007
-#define regk_iop_sw_cfg_spu1_gioout8              0x0000000f
-#define regk_iop_sw_cfg_spu1_gioout9              0x0000000f
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr0      0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp0_tmr1      0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr0      0x00000001
-#define regk_iop_sw_cfg_strb_timer_grp1_tmr1      0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr0      0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp2_tmr1      0x00000002
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr0      0x00000003
-#define regk_iop_sw_cfg_strb_timer_grp3_tmr1      0x00000002
-#define regk_iop_sw_cfg_timer_grp0                0x00000000
-#define regk_iop_sw_cfg_timer_grp0_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp0_strb0          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb1          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb2          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_strb3          0x0000000a
-#define regk_iop_sw_cfg_timer_grp0_tmr0           0x00000004
-#define regk_iop_sw_cfg_timer_grp0_tmr1           0x00000004
-#define regk_iop_sw_cfg_timer_grp1                0x00000000
-#define regk_iop_sw_cfg_timer_grp1_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp1_strb0          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb1          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb2          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_strb3          0x0000000b
-#define regk_iop_sw_cfg_timer_grp1_tmr0           0x00000005
-#define regk_iop_sw_cfg_timer_grp1_tmr1           0x00000005
-#define regk_iop_sw_cfg_timer_grp2                0x00000000
-#define regk_iop_sw_cfg_timer_grp2_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp2_strb0          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb1          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb2          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_strb3          0x0000000c
-#define regk_iop_sw_cfg_timer_grp2_tmr0           0x00000006
-#define regk_iop_sw_cfg_timer_grp2_tmr1           0x00000006
-#define regk_iop_sw_cfg_timer_grp3                0x00000000
-#define regk_iop_sw_cfg_timer_grp3_rot            0x00000001
-#define regk_iop_sw_cfg_timer_grp3_strb0          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb1          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb2          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_strb3          0x0000000d
-#define regk_iop_sw_cfg_timer_grp3_tmr0           0x00000007
-#define regk_iop_sw_cfg_timer_grp3_tmr1           0x00000007
-#define regk_iop_sw_cfg_trig0_0                   0x00000000
-#define regk_iop_sw_cfg_trig0_1                   0x00000000
-#define regk_iop_sw_cfg_trig0_2                   0x00000000
-#define regk_iop_sw_cfg_trig0_3                   0x00000000
-#define regk_iop_sw_cfg_trig1_0                   0x00000000
-#define regk_iop_sw_cfg_trig1_1                   0x00000000
-#define regk_iop_sw_cfg_trig1_2                   0x00000000
-#define regk_iop_sw_cfg_trig1_3                   0x00000000
-#define regk_iop_sw_cfg_trig2_0                   0x00000000
-#define regk_iop_sw_cfg_trig2_1                   0x00000000
-#define regk_iop_sw_cfg_trig2_2                   0x00000000
-#define regk_iop_sw_cfg_trig2_3                   0x00000000
-#define regk_iop_sw_cfg_trig3_0                   0x00000000
-#define regk_iop_sw_cfg_trig3_1                   0x00000000
-#define regk_iop_sw_cfg_trig3_2                   0x00000000
-#define regk_iop_sw_cfg_trig3_3                   0x00000000
-#define regk_iop_sw_cfg_trig4_0                   0x00000001
-#define regk_iop_sw_cfg_trig4_1                   0x00000001
-#define regk_iop_sw_cfg_trig4_2                   0x00000001
-#define regk_iop_sw_cfg_trig4_3                   0x00000001
-#define regk_iop_sw_cfg_trig5_0                   0x00000001
-#define regk_iop_sw_cfg_trig5_1                   0x00000001
-#define regk_iop_sw_cfg_trig5_2                   0x00000001
-#define regk_iop_sw_cfg_trig5_3                   0x00000001
-#define regk_iop_sw_cfg_trig6_0                   0x00000001
-#define regk_iop_sw_cfg_trig6_1                   0x00000001
-#define regk_iop_sw_cfg_trig6_2                   0x00000001
-#define regk_iop_sw_cfg_trig6_3                   0x00000001
-#define regk_iop_sw_cfg_trig7_0                   0x00000001
-#define regk_iop_sw_cfg_trig7_1                   0x00000001
-#define regk_iop_sw_cfg_trig7_2                   0x00000001
-#define regk_iop_sw_cfg_trig7_3                   0x00000001
-#endif /* __iop_sw_cfg_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
deleted file mode 100644
index ef04a57a0680..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_cpu_defs_asm.h
+++ /dev/null
@@ -1,1759 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_cpu_defs_asm_h
-#define __iop_sw_cpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_cpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_cpu.r
- *      id: $Id: iop_sw_cpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_cpu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_cpu_rw_mc_data___val___width 32
-#define reg_iop_sw_cpu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_cpu, type rs */
-#define reg_iop_sw_cpu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_cpu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_cpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_cpu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_cpu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_gio_in_offset 80
-
-/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_intr0_mask___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_intr0_mask_offset 84
-
-/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr0_offset 88
-
-/* Register r_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_intr0_offset 92
-
-/* Register r_masked_intr0, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_2___bit 18
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_3___bit 19
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_4___bit 20
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_5___bit 21
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_6___bit 22
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu0_7___bit 23
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_8___bit 24
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_9___bit 25
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_10___bit 26
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_11___bit 27
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_12___bit 28
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_13___bit 29
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_14___bit 30
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr0___spu1_15___bit 31
-#define reg_iop_sw_cpu_r_masked_intr0_offset 96
-
-/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr1_mask___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_intr1_mask_offset 100
-
-/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_rw_ack_intr1_offset 104
-
-/* Register r_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_intr1_offset 108
-
-/* Register r_masked_intr1, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_8___bit 16
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_9___bit 17
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_10___bit 18
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_11___bit 19
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_12___bit 20
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_13___bit 21
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_14___bit 22
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu0_15___bit 23
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_0___bit 24
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_1___bit 25
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_2___bit 26
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_3___bit 27
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_4___bit 28
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_5___bit 29
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_6___bit 30
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr1___spu1_7___bit 31
-#define reg_iop_sw_cpu_r_masked_intr1_offset 112
-
-/* Register rw_intr2_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_in0___bit 16
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___dmc_out0___bit 17
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0___bit 18
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0___bit 19
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp0___bit 30
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr2_mask___timer_grp1___bit 31
-#define reg_iop_sw_cpu_rw_intr2_mask_offset 116
-
-/* Register rw_ack_intr2, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr2_offset 120
-
-/* Register r_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_intr2_offset 124
-
-/* Register r_masked_intr2, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_0___bit 0
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_1___bit 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_2___bit 2
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_3___bit 3
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_4___bit 4
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_5___bit 5
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_6___bit 6
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___mpu_7___bit 7
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___spu0_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_in0___bit 16
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___dmc_out0___bit 17
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0___bit 18
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0___bit 19
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_in0_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___fifo_out0_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp0___bit 30
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr2___timer_grp1___bit 31
-#define reg_iop_sw_cpu_r_masked_intr2_offset 128
-
-/* Register rw_intr3_mask, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_in1___bit 16
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___dmc_out1___bit 17
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1___bit 18
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1___bit 19
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp2___bit 30
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___width 1
-#define reg_iop_sw_cpu_rw_intr3_mask___timer_grp3___bit 31
-#define reg_iop_sw_cpu_rw_intr3_mask_offset 132
-
-/* Register rw_ack_intr3, scope iop_sw_cpu, type rw */
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_rw_ack_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_rw_ack_intr3_offset 136
-
-/* Register r_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_intr3_offset 140
-
-/* Register r_masked_intr3, scope iop_sw_cpu, type r */
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___lsb 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_16___bit 0
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___lsb 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_17___bit 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___lsb 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_18___bit 2
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___lsb 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_19___bit 3
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___lsb 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_20___bit 4
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___lsb 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_21___bit 5
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___lsb 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_22___bit 6
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___lsb 7
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___mpu_23___bit 7
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___lsb 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_0___bit 8
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___lsb 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_1___bit 9
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___lsb 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_2___bit 10
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___lsb 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_3___bit 11
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___lsb 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_4___bit 12
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___lsb 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_5___bit 13
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___lsb 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_6___bit 14
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___lsb 15
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___spu1_7___bit 15
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___lsb 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_in1___bit 16
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___lsb 17
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___dmc_out1___bit 17
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___lsb 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1___bit 18
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___lsb 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1___bit 19
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___lsb 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_in1_extra___bit 20
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___lsb 21
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___fifo_out1_extra___bit 21
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___lsb 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp0___bit 22
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___lsb 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp1___bit 23
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___lsb 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp2___bit 24
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___lsb 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp3___bit 25
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___lsb 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp4___bit 26
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___lsb 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp5___bit 27
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___lsb 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp6___bit 28
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___lsb 29
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___trigger_grp7___bit 29
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___lsb 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp2___bit 30
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___lsb 31
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___width 1
-#define reg_iop_sw_cpu_r_masked_intr3___timer_grp3___bit 31
-#define reg_iop_sw_cpu_r_masked_intr3_offset 144
-
-
-/* Constants */
-#define regk_iop_sw_cpu_copy                      0x00000000
-#define regk_iop_sw_cpu_no                        0x00000000
-#define regk_iop_sw_cpu_rd                        0x00000002
-#define regk_iop_sw_cpu_reg_copy                  0x00000001
-#define regk_iop_sw_cpu_rw_bus0_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus0_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus0_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_bus1_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_cpu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_cpu_rw_intr0_mask_default     0x00000000
-#define regk_iop_sw_cpu_rw_intr1_mask_default     0x00000000
-#define regk_iop_sw_cpu_rw_intr2_mask_default     0x00000000
-#define regk_iop_sw_cpu_rw_intr3_mask_default     0x00000000
-#define regk_iop_sw_cpu_wr                        0x00000003
-#define regk_iop_sw_cpu_yes                       0x00000001
-#endif /* __iop_sw_cpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
deleted file mode 100644
index 22292069e4fd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_mpu_defs_asm.h
+++ /dev/null
@@ -1,1777 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_mpu_defs_asm_h
-#define __iop_sw_mpu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_mpu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_mpu.r
- *      id: $Id: iop_sw_mpu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0
-#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2
-#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0
-
-/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_mpu_rw_mc_ctrl_offset 4
-
-/* Register rw_mc_data, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_mpu_rw_mc_data___val___width 32
-#define reg_iop_sw_mpu_rw_mc_data_offset 8
-
-/* Register rw_mc_addr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_mc_addr_offset 12
-
-/* Register rs_mc_data, scope iop_sw_mpu, type rs */
-#define reg_iop_sw_mpu_rs_mc_data_offset 16
-
-/* Register r_mc_data, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_data_offset 20
-
-/* Register r_mc_stat, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_mpu_r_mc_stat_offset 24
-
-/* Register rw_bus0_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_clr_mask_offset 28
-
-/* Register rw_bus0_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus0_set_mask_offset 32
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_clr_mask_offset 36
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus0_oe_set_mask_offset 40
-
-/* Register r_bus0_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus0_in_offset 44
-
-/* Register rw_bus1_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_clr_mask_offset 48
-
-/* Register rw_bus1_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_mpu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_mpu_rw_bus1_set_mask_offset 52
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_clr_mask_offset 56
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_mpu_rw_bus1_oe_set_mask_offset 60
-
-/* Register r_bus1_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_bus1_in_offset 64
-
-/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 68
-
-/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_set_mask_offset 72
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 76
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 80
-
-/* Register r_gio_in, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_gio_in_offset 84
-
-/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_rw_cpu_intr_offset 88
-
-/* Register r_cpu_intr, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1
-#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31
-#define reg_iop_sw_mpu_r_cpu_intr_offset 92
-
-/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 96
-
-/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 100
-
-/* Register r_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp0_offset 104
-
-/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr0___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr0___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp4___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr1___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr1___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp5___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr2___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr2___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp6___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu0_intr3___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___spu1_intr3___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp7___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 108
-
-/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 112
-
-/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 116
-
-/* Register r_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp1_offset 120
-
-/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr4___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr4___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in0_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr5___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr5___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr6___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr6___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in1_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu0_intr7___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___spu1_intr7___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 124
-
-/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 128
-
-/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 132
-
-/* Register r_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp2_offset 136
-
-/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr8___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr8___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp6___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr9___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr9___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp7___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in1_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr10___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr10___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp4___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu0_intr11___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___spu1_intr11___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp5___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in0_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 140
-
-/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 4
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1___bit 5
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out0___bit 7
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 12
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0___bit 13
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in0___bit 15
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp2___bit 20
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0___bit 21
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out1___bit 23
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp3___bit 28
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1___bit 29
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___width 1
-#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in1___bit 31
-#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 144
-
-/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 148
-
-/* Register r_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_intr_grp3_offset 152
-
-/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___lsb 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr12___bit 0
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___lsb 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr12___bit 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___lsb 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp0___bit 2
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 3
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 4
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___lsb 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1___bit 5
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___lsb 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in1_extra___bit 6
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___lsb 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out0___bit 7
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___lsb 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr13___bit 8
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___lsb 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr13___bit 9
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___lsb 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp1___bit 10
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 11
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 12
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___lsb 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0___bit 13
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___lsb 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out0_extra___bit 14
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___lsb 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in0___bit 15
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___lsb 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr14___bit 16
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___lsb 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr14___bit 17
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___lsb 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp2___bit 18
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 19
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___lsb 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp2___bit 20
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___lsb 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0___bit 21
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___lsb 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in0_extra___bit 22
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___lsb 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out1___bit 23
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___lsb 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu0_intr15___bit 24
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___lsb 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___spu1_intr15___bit 25
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___lsb 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp3___bit 26
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 27
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___lsb 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp3___bit 28
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___lsb 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1___bit 29
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___lsb 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out1_extra___bit 30
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___lsb 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___width 1
-#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in1___bit 31
-#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 156
-
-
-/* Constants */
-#define regk_iop_sw_mpu_copy                      0x00000000
-#define regk_iop_sw_mpu_cpu                       0x00000000
-#define regk_iop_sw_mpu_mpu                       0x00000001
-#define regk_iop_sw_mpu_no                        0x00000000
-#define regk_iop_sw_mpu_nop                       0x00000000
-#define regk_iop_sw_mpu_rd                        0x00000002
-#define regk_iop_sw_mpu_reg_copy                  0x00000001
-#define regk_iop_sw_mpu_rw_bus0_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus0_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus0_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_bus1_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp0_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp1_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp2_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_intr_grp3_mask_default  0x00000000
-#define regk_iop_sw_mpu_rw_sw_cfg_owner_default   0x00000000
-#define regk_iop_sw_mpu_set                       0x00000001
-#define regk_iop_sw_mpu_spu0                      0x00000002
-#define regk_iop_sw_mpu_spu1                      0x00000003
-#define regk_iop_sw_mpu_wr                        0x00000003
-#define regk_iop_sw_mpu_yes                       0x00000001
-#endif /* __iop_sw_mpu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h
deleted file mode 100644
index 82729218621c..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_sw_spu_defs_asm.h
+++ /dev/null
@@ -1,692 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_sw_spu_defs_asm_h
-#define __iop_sw_spu_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- *     id:           <not found>
- *     last modfied: Mon Apr 11 16:10:19 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_sw_spu_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_sw_spu.r
- *      id: $Id: iop_sw_spu_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1
-#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2
-#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3
-#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___lsb 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu0_mem___bit 6
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___lsb 7
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___width 1
-#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu1_mem___bit 7
-#define reg_iop_sw_spu_rw_mc_ctrl_offset 0
-
-/* Register rw_mc_data, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_data___val___lsb 0
-#define reg_iop_sw_spu_rw_mc_data___val___width 32
-#define reg_iop_sw_spu_rw_mc_data_offset 4
-
-/* Register rw_mc_addr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mc_addr_offset 8
-
-/* Register rs_mc_data, scope iop_sw_spu, type rs */
-#define reg_iop_sw_spu_rs_mc_data_offset 12
-
-/* Register r_mc_data, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_data_offset 16
-
-/* Register r_mc_stat, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___lsb 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu0___bit 2
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___lsb 3
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___busy_spu1___bit 3
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 4
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 5
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___lsb 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu0___bit 6
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___lsb 7
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___width 1
-#define reg_iop_sw_spu_r_mc_stat___owned_by_spu1___bit 7
-#define reg_iop_sw_spu_r_mc_stat_offset 20
-
-/* Register rw_bus0_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_offset 24
-
-/* Register rw_bus0_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus0_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_offset 28
-
-/* Register rw_bus0_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_clr_mask_offset 32
-
-/* Register rw_bus0_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus0_oe_set_mask_offset 36
-
-/* Register r_bus0_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus0_in_offset 40
-
-/* Register rw_bus1_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_clr_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_offset 44
-
-/* Register rw_bus1_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___lsb 16
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___lsb 24
-#define reg_iop_sw_spu_rw_bus1_set_mask___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_offset 48
-
-/* Register rw_bus1_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_clr_mask_offset 52
-
-/* Register rw_bus1_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte0___bit 0
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___lsb 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte1___bit 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___lsb 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte2___bit 2
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___lsb 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___width 1
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask___byte3___bit 3
-#define reg_iop_sw_spu_rw_bus1_oe_set_mask_offset 56
-
-/* Register r_bus1_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_bus1_in_offset 60
-
-/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_clr_mask_offset 64
-
-/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_set_mask_offset 68
-
-/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 72
-
-/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 76
-
-/* Register r_gio_in, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_gio_in_offset 80
-
-/* Register rw_bus0_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_lo_offset 84
-
-/* Register rw_bus0_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_clr_mask_hi_offset 88
-
-/* Register rw_bus0_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_lo_offset 92
-
-/* Register rw_bus0_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus0_set_mask_hi_offset 96
-
-/* Register rw_bus1_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_lo_offset 100
-
-/* Register rw_bus1_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_clr_mask_hi_offset 104
-
-/* Register rw_bus1_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte0___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo___byte1___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_lo_offset 108
-
-/* Register rw_bus1_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___lsb 0
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte2___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___lsb 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi___byte3___width 8
-#define reg_iop_sw_spu_rw_bus1_set_mask_hi_offset 112
-
-/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 116
-
-/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 120
-
-/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 124
-
-/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 128
-
-/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 132
-
-/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 136
-
-/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 140
-
-/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16
-#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 144
-
-/* Register rw_cpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_cpu_intr_offset 148
-
-/* Register r_cpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_cpu_intr_offset 152
-
-/* Register r_hw_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1
-#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___lsb 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp2___bit 10
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___lsb 11
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___width 1
-#define reg_iop_sw_spu_r_hw_intr___timer_grp3___bit 11
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___lsb 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0___bit 12
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___lsb 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out0_extra___bit 13
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___lsb 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0___bit 14
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___lsb 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in0_extra___bit 15
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___lsb 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1___bit 16
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___lsb 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_out1_extra___bit 17
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___lsb 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1___bit 18
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___lsb 19
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___width 1
-#define reg_iop_sw_spu_r_hw_intr___fifo_in1_extra___bit 19
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___lsb 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out0___bit 20
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___lsb 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in0___bit 21
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___lsb 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_out1___bit 22
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___lsb 23
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___width 1
-#define reg_iop_sw_spu_r_hw_intr___dmc_in1___bit 23
-#define reg_iop_sw_spu_r_hw_intr_offset 156
-
-/* Register rw_mpu_intr, scope iop_sw_spu, type rw */
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_rw_mpu_intr_offset 160
-
-/* Register r_mpu_intr, scope iop_sw_spu, type r */
-#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0
-#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0
-#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2
-#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2
-#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3
-#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3
-#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4
-#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4
-#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5
-#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5
-#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6
-#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6
-#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7
-#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7
-#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8
-#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8
-#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9
-#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9
-#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10
-#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10
-#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11
-#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11
-#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12
-#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12
-#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13
-#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13
-#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14
-#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14
-#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15
-#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___lsb 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr0___bit 16
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___lsb 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr1___bit 17
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___lsb 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr2___bit 18
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___lsb 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr3___bit 19
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___lsb 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr4___bit 20
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___lsb 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr5___bit 21
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___lsb 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr6___bit 22
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___lsb 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr7___bit 23
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___lsb 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr8___bit 24
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___lsb 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr9___bit 25
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___lsb 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr10___bit 26
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___lsb 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr11___bit 27
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___lsb 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr12___bit 28
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___lsb 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr13___bit 29
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___lsb 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr14___bit 30
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___lsb 31
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___width 1
-#define reg_iop_sw_spu_r_mpu_intr___other_spu_intr15___bit 31
-#define reg_iop_sw_spu_r_mpu_intr_offset 164
-
-
-/* Constants */
-#define regk_iop_sw_spu_copy                      0x00000000
-#define regk_iop_sw_spu_no                        0x00000000
-#define regk_iop_sw_spu_nop                       0x00000000
-#define regk_iop_sw_spu_rd                        0x00000002
-#define regk_iop_sw_spu_reg_copy                  0x00000001
-#define regk_iop_sw_spu_rw_bus0_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus0_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus0_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_bus1_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_clr_mask_default   0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_oe_set_mask_default  0x00000000
-#define regk_iop_sw_spu_rw_gio_set_mask_default   0x00000000
-#define regk_iop_sw_spu_set                       0x00000001
-#define regk_iop_sw_spu_wr                        0x00000003
-#define regk_iop_sw_spu_yes                       0x00000001
-#endif /* __iop_sw_spu_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h
deleted file mode 100644
index 4f1cf73d86cd..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_timer_grp_defs_asm.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_timer_grp_defs_asm_h
-#define __iop_timer_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_timer_grp.r
- *     id:           iop_timer_grp.r,v 1.29 2005/02/16 09:13:27 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_timer_grp_defs_asm.h ../../inst/io_proc/rtl/iop_timer_grp.r
- *      id: $Id: iop_timer_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register rw_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_cfg___clk_src___width 1
-#define reg_iop_timer_grp_rw_cfg___clk_src___bit 0
-#define reg_iop_timer_grp_rw_cfg___trig___lsb 1
-#define reg_iop_timer_grp_rw_cfg___trig___width 2
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___lsb 3
-#define reg_iop_timer_grp_rw_cfg___clk_gen_div___width 8
-#define reg_iop_timer_grp_rw_cfg___clk_div___lsb 11
-#define reg_iop_timer_grp_rw_cfg___clk_div___width 8
-#define reg_iop_timer_grp_rw_cfg_offset 0
-
-/* Register rw_half_period, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period___quota_lo___lsb 0
-#define reg_iop_timer_grp_rw_half_period___quota_lo___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___lsb 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi___width 15
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___lsb 30
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___width 1
-#define reg_iop_timer_grp_rw_half_period___quota_hi_sel___bit 30
-#define reg_iop_timer_grp_rw_half_period_offset 4
-
-/* Register rw_half_period_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_half_period_len_offset 8
-
-#define STRIDE_iop_timer_grp_rw_tmr_cfg 4
-/* Register rw_tmr_cfg, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___lsb 0
-#define reg_iop_timer_grp_rw_tmr_cfg___clk_src___width 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___lsb 3
-#define reg_iop_timer_grp_rw_tmr_cfg___strb___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___lsb 5
-#define reg_iop_timer_grp_rw_tmr_cfg___run_mode___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___lsb 7
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___out_mode___bit 7
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___lsb 8
-#define reg_iop_timer_grp_rw_tmr_cfg___active_on_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___lsb 10
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___inv___bit 10
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___lsb 11
-#define reg_iop_timer_grp_rw_tmr_cfg___en_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___lsb 13
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_by_tmr___width 2
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___lsb 15
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___en_only_by_reg___bit 15
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___lsb 16
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___dis_only_by_reg___bit 16
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___lsb 17
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___width 1
-#define reg_iop_timer_grp_rw_tmr_cfg___rst_at_en_strb___bit 17
-#define reg_iop_timer_grp_rw_tmr_cfg_offset 12
-
-#define STRIDE_iop_timer_grp_rw_tmr_len 4
-/* Register rw_tmr_len, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_tmr_len___val___lsb 0
-#define reg_iop_timer_grp_rw_tmr_len___val___width 16
-#define reg_iop_timer_grp_rw_tmr_len_offset 44
-
-/* Register rw_cmd, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_cmd___rst___lsb 0
-#define reg_iop_timer_grp_rw_cmd___rst___width 4
-#define reg_iop_timer_grp_rw_cmd___en___lsb 4
-#define reg_iop_timer_grp_rw_cmd___en___width 4
-#define reg_iop_timer_grp_rw_cmd___dis___lsb 8
-#define reg_iop_timer_grp_rw_cmd___dis___width 4
-#define reg_iop_timer_grp_rw_cmd___strb___lsb 12
-#define reg_iop_timer_grp_rw_cmd___strb___width 4
-#define reg_iop_timer_grp_rw_cmd_offset 60
-
-/* Register r_clk_gen_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_clk_gen_cnt_offset 64
-
-#define STRIDE_iop_timer_grp_rs_tmr_cnt 8
-/* Register rs_tmr_cnt, scope iop_timer_grp, type rs */
-#define reg_iop_timer_grp_rs_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_rs_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_rs_tmr_cnt_offset 68
-
-#define STRIDE_iop_timer_grp_r_tmr_cnt 8
-/* Register r_tmr_cnt, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_tmr_cnt___val___lsb 0
-#define reg_iop_timer_grp_r_tmr_cnt___val___width 16
-#define reg_iop_timer_grp_r_tmr_cnt_offset 72
-
-/* Register rw_intr_mask, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr0___bit 0
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr1___bit 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr2___bit 2
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___width 1
-#define reg_iop_timer_grp_rw_intr_mask___tmr3___bit 3
-#define reg_iop_timer_grp_rw_intr_mask_offset 100
-
-/* Register rw_ack_intr, scope iop_timer_grp, type rw */
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr0___bit 0
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr1___bit 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr2___bit 2
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___width 1
-#define reg_iop_timer_grp_rw_ack_intr___tmr3___bit 3
-#define reg_iop_timer_grp_rw_ack_intr_offset 104
-
-/* Register r_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_intr_offset 108
-
-/* Register r_masked_intr, scope iop_timer_grp, type r */
-#define reg_iop_timer_grp_r_masked_intr___tmr0___lsb 0
-#define reg_iop_timer_grp_r_masked_intr___tmr0___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr0___bit 0
-#define reg_iop_timer_grp_r_masked_intr___tmr1___lsb 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr1___bit 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___lsb 2
-#define reg_iop_timer_grp_r_masked_intr___tmr2___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr2___bit 2
-#define reg_iop_timer_grp_r_masked_intr___tmr3___lsb 3
-#define reg_iop_timer_grp_r_masked_intr___tmr3___width 1
-#define reg_iop_timer_grp_r_masked_intr___tmr3___bit 3
-#define reg_iop_timer_grp_r_masked_intr_offset 112
-
-
-/* Constants */
-#define regk_iop_timer_grp_clk200                 0x00000000
-#define regk_iop_timer_grp_clk_gen                0x00000002
-#define regk_iop_timer_grp_complete               0x00000002
-#define regk_iop_timer_grp_div_clk200             0x00000001
-#define regk_iop_timer_grp_div_clk_gen            0x00000003
-#define regk_iop_timer_grp_ext                    0x00000001
-#define regk_iop_timer_grp_hi                     0x00000000
-#define regk_iop_timer_grp_long_period            0x00000001
-#define regk_iop_timer_grp_neg                    0x00000002
-#define regk_iop_timer_grp_no                     0x00000000
-#define regk_iop_timer_grp_once                   0x00000003
-#define regk_iop_timer_grp_pause                  0x00000001
-#define regk_iop_timer_grp_pos                    0x00000001
-#define regk_iop_timer_grp_pos_neg                0x00000003
-#define regk_iop_timer_grp_pulse                  0x00000000
-#define regk_iop_timer_grp_r_tmr_cnt_size         0x00000004
-#define regk_iop_timer_grp_rs_tmr_cnt_size        0x00000004
-#define regk_iop_timer_grp_rw_cfg_default         0x00000002
-#define regk_iop_timer_grp_rw_intr_mask_default   0x00000000
-#define regk_iop_timer_grp_rw_tmr_cfg_default0    0x00018000
-#define regk_iop_timer_grp_rw_tmr_cfg_default1    0x0001a900
-#define regk_iop_timer_grp_rw_tmr_cfg_default2    0x0001d200
-#define regk_iop_timer_grp_rw_tmr_cfg_default3    0x0001fb00
-#define regk_iop_timer_grp_rw_tmr_cfg_size        0x00000004
-#define regk_iop_timer_grp_rw_tmr_len_default     0x00000000
-#define regk_iop_timer_grp_rw_tmr_len_size        0x00000004
-#define regk_iop_timer_grp_short_period           0x00000000
-#define regk_iop_timer_grp_stop                   0x00000000
-#define regk_iop_timer_grp_tmr                    0x00000004
-#define regk_iop_timer_grp_toggle                 0x00000001
-#define regk_iop_timer_grp_yes                    0x00000001
-#endif /* __iop_timer_grp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
deleted file mode 100644
index 7bc882c62952..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_trigger_grp_defs_asm.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_trigger_grp_defs_asm_h
-#define __iop_trigger_grp_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/iop_trigger_grp.r
- *     id:           iop_trigger_grp.r,v 0.20 2005/02/16 09:13:20 niklaspa Exp
- *     last modfied: Mon Apr 11 16:08:46 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_trigger_grp_defs_asm.h ../../inst/io_proc/rtl/iop_trigger_grp.r
- *      id: $Id: iop_trigger_grp_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-#define STRIDE_iop_trigger_grp_rw_cfg 4
-/* Register rw_cfg, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cfg___action___lsb 0
-#define reg_iop_trigger_grp_rw_cfg___action___width 2
-#define reg_iop_trigger_grp_rw_cfg___once___lsb 2
-#define reg_iop_trigger_grp_rw_cfg___once___width 1
-#define reg_iop_trigger_grp_rw_cfg___once___bit 2
-#define reg_iop_trigger_grp_rw_cfg___trig___lsb 3
-#define reg_iop_trigger_grp_rw_cfg___trig___width 3
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___lsb 6
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___en_only_by_reg___bit 6
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___lsb 7
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___width 1
-#define reg_iop_trigger_grp_rw_cfg___dis_only_by_reg___bit 7
-#define reg_iop_trigger_grp_rw_cfg_offset 0
-
-/* Register rw_cmd, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_cmd___dis___lsb 0
-#define reg_iop_trigger_grp_rw_cmd___dis___width 4
-#define reg_iop_trigger_grp_rw_cmd___en___lsb 4
-#define reg_iop_trigger_grp_rw_cmd___en___width 4
-#define reg_iop_trigger_grp_rw_cmd_offset 16
-
-/* Register rw_intr_mask, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig0___bit 0
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig1___bit 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig2___bit 2
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___width 1
-#define reg_iop_trigger_grp_rw_intr_mask___trig3___bit 3
-#define reg_iop_trigger_grp_rw_intr_mask_offset 20
-
-/* Register rw_ack_intr, scope iop_trigger_grp, type rw */
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig0___bit 0
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig1___bit 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig2___bit 2
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___width 1
-#define reg_iop_trigger_grp_rw_ack_intr___trig3___bit 3
-#define reg_iop_trigger_grp_rw_ack_intr_offset 24
-
-/* Register r_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_intr_offset 28
-
-/* Register r_masked_intr, scope iop_trigger_grp, type r */
-#define reg_iop_trigger_grp_r_masked_intr___trig0___lsb 0
-#define reg_iop_trigger_grp_r_masked_intr___trig0___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig0___bit 0
-#define reg_iop_trigger_grp_r_masked_intr___trig1___lsb 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig1___bit 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___lsb 2
-#define reg_iop_trigger_grp_r_masked_intr___trig2___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig2___bit 2
-#define reg_iop_trigger_grp_r_masked_intr___trig3___lsb 3
-#define reg_iop_trigger_grp_r_masked_intr___trig3___width 1
-#define reg_iop_trigger_grp_r_masked_intr___trig3___bit 3
-#define reg_iop_trigger_grp_r_masked_intr_offset 32
-
-
-/* Constants */
-#define regk_iop_trigger_grp_fall                 0x00000002
-#define regk_iop_trigger_grp_fall_lo              0x00000006
-#define regk_iop_trigger_grp_no                   0x00000000
-#define regk_iop_trigger_grp_off                  0x00000000
-#define regk_iop_trigger_grp_pulse                0x00000000
-#define regk_iop_trigger_grp_rise                 0x00000001
-#define regk_iop_trigger_grp_rise_fall            0x00000003
-#define regk_iop_trigger_grp_rise_fall_hi         0x00000007
-#define regk_iop_trigger_grp_rise_fall_lo         0x00000004
-#define regk_iop_trigger_grp_rise_hi              0x00000005
-#define regk_iop_trigger_grp_rw_cfg_default       0x000000c0
-#define regk_iop_trigger_grp_rw_cfg_size          0x00000004
-#define regk_iop_trigger_grp_rw_intr_mask_default  0x00000000
-#define regk_iop_trigger_grp_toggle               0x00000003
-#define regk_iop_trigger_grp_yes                  0x00000001
-#endif /* __iop_trigger_grp_defs_asm_h */
diff --git a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h
deleted file mode 100644
index 2e239957e34a..000000000000
--- a/arch/cris/include/arch-v32/arch/hwregs/iop/asm/iop_version_defs_asm.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __iop_version_defs_asm_h
-#define __iop_version_defs_asm_h
-
-/*
- * This file is autogenerated from
- *   file:           ../../inst/io_proc/rtl/guinness/iop_version.r
- *     id:           iop_version.r,v 1.3 2004/04/22 12:37:54 jonaso Exp
- *     last modfied: Mon Apr 11 16:08:44 2005
- *
- *   by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/iop_version_defs_asm.h ../../inst/io_proc/rtl/guinness/iop_version.r
- *      id: $Id: iop_version_defs_asm.h,v 1.5 2005/04/24 18:31:07 starvik Exp $
- * Any changes here will be lost.
- *
- * -*- buffer-read-only: t -*-
- */
-
-#ifndef REG_FIELD
-#define REG_FIELD( scope, reg, field, value ) \
-  REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_FIELD_X_( value, shift ) ((value) << shift)
-#endif
-
-#ifndef REG_STATE
-#define REG_STATE( scope, reg, field, symbolic_value ) \
-  REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb )
-#define REG_STATE_X_( k, shift ) (k << shift)
-#endif
-
-#ifndef REG_MASK
-#define REG_MASK( scope, reg, field ) \
-  REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb )
-#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb)
-#endif
-
-#ifndef REG_LSB
-#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb
-#endif
-
-#ifndef REG_BIT
-#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit
-#endif
-
-#ifndef REG_ADDR
-#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset)
-#define REG_ADDR_X_( inst, offs ) ((inst) + offs)
-#endif
-
-#ifndef REG_ADDR_VECT
-#define REG_ADDR_VECT( scope, inst, reg, index ) \
-         REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \
-			 STRIDE_##scope##_##reg )
-#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \
-                          ((inst) + offs + (index) * stride)
-#endif
-
-/* Register r_version, scope iop_version, type r */
-#define reg_iop_version_r_version___nr___lsb 0
-#define reg_iop_version_r_version___nr___width 8
-#define reg_iop_version_r_version_offset 0
-
-
-/* Constants */
-#define regk_iop_version_v1_0                     0x00000001
-#endif /* __iop_version_defs_asm_h */