diff options
| author | Jesper Nilsson <jesper@jni.nu> | 2018-03-11 11:05:23 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2018-03-16 10:56:05 +0100 |
| commit | c690eddc2f3b44b24520f4a77cc3a4c9bde7d571 (patch) | |
| tree | b7ba2caa6ebb2e36a529f9bf7182c9e0a73d53c4 /arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop | |
| parent | bb9d812643d8a121df7d614a2b9c60193a92deb0 (diff) | |
CRIS: Drop support for the CRIS port
The port was added back in 2000 so it's no longer even a good source
of inspiration for newer ports (if it ever was)
The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008.
Coupled with time and working developer board hardware being
in low supply, it's time to drop the port from Linux.
So long and thanks for all the fish!
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop')
16 files changed, 0 insertions, 6626 deletions
diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h deleted file mode 100644 index 5e5f4d94aecf..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_reg_space_asm.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define iop_version 0 -#define iop_fifo_in_extra 64 -#define iop_fifo_out_extra 128 -#define iop_trigger_grp0 192 -#define iop_trigger_grp1 256 -#define iop_trigger_grp2 320 -#define iop_trigger_grp3 384 -#define iop_trigger_grp4 448 -#define iop_trigger_grp5 512 -#define iop_trigger_grp6 576 -#define iop_trigger_grp7 640 -#define iop_crc_par 768 -#define iop_dmc_in 896 -#define iop_dmc_out 1024 -#define iop_fifo_in 1152 -#define iop_fifo_out 1280 -#define iop_scrc_in 1408 -#define iop_scrc_out 1536 -#define iop_timer_grp0 1664 -#define iop_timer_grp1 1792 -#define iop_sap_in 2048 -#define iop_sap_out 2304 -#define iop_spu 2560 -#define iop_sw_cfg 2816 -#define iop_sw_cpu 3072 -#define iop_sw_mpu 3328 -#define iop_sw_spu 3584 -#define iop_mpu 4096 diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h deleted file mode 100644 index ee0587ec433c..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_in_defs_asm.h +++ /dev/null @@ -1,110 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_in_defs_asm_h -#define __iop_sap_in_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_in_defs_asm.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_bus_byte___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_bus_byte___sync_sel___width 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_bus_byte___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_bus_byte___sync_edge___width 2 -#define reg_iop_sap_in_rw_bus_byte___delay___lsb 7 -#define reg_iop_sap_in_rw_bus_byte___delay___width 2 -#define reg_iop_sap_in_rw_bus_byte_offset 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -#define reg_iop_sap_in_rw_gio___sync_sel___lsb 0 -#define reg_iop_sap_in_rw_gio___sync_sel___width 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___lsb 2 -#define reg_iop_sap_in_rw_gio___sync_ext_src___width 3 -#define reg_iop_sap_in_rw_gio___sync_edge___lsb 5 -#define reg_iop_sap_in_rw_gio___sync_edge___width 2 -#define reg_iop_sap_in_rw_gio___delay___lsb 7 -#define reg_iop_sap_in_rw_gio___delay___width 2 -#define reg_iop_sap_in_rw_gio___logic___lsb 9 -#define reg_iop_sap_in_rw_gio___logic___width 2 -#define reg_iop_sap_in_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_in_and 0x00000002 -#define regk_iop_sap_in_ext_clk200 0x00000003 -#define regk_iop_sap_in_gio0 0x00000000 -#define regk_iop_sap_in_gio12 0x00000003 -#define regk_iop_sap_in_gio16 0x00000004 -#define regk_iop_sap_in_gio20 0x00000005 -#define regk_iop_sap_in_gio24 0x00000006 -#define regk_iop_sap_in_gio28 0x00000007 -#define regk_iop_sap_in_gio4 0x00000001 -#define regk_iop_sap_in_gio8 0x00000002 -#define regk_iop_sap_in_inv 0x00000001 -#define regk_iop_sap_in_neg 0x00000002 -#define regk_iop_sap_in_no 0x00000000 -#define regk_iop_sap_in_no_del_ext_clk200 0x00000002 -#define regk_iop_sap_in_none 0x00000000 -#define regk_iop_sap_in_one 0x00000001 -#define regk_iop_sap_in_or 0x00000003 -#define regk_iop_sap_in_pos 0x00000001 -#define regk_iop_sap_in_pos_neg 0x00000003 -#define regk_iop_sap_in_rw_bus_byte_default 0x00000000 -#define regk_iop_sap_in_rw_bus_byte_size 0x00000004 -#define regk_iop_sap_in_rw_gio_default 0x00000000 -#define regk_iop_sap_in_rw_gio_size 0x00000020 -#define regk_iop_sap_in_timer_grp0_tmr3 0x00000000 -#define regk_iop_sap_in_timer_grp1_tmr3 0x00000001 -#define regk_iop_sap_in_tmr_clk200 0x00000001 -#define regk_iop_sap_in_two 0x00000002 -#define regk_iop_sap_in_two_clk200 0x00000000 -#endif /* __iop_sap_in_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h deleted file mode 100644 index 9bbe0b920c93..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sap_out_defs_asm.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_out_defs_asm_h -#define __iop_sap_out_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sap_out_defs_asm.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gen_gated___clk0_src___lsb 0 -#define reg_iop_sap_out_rw_gen_gated___clk0_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___lsb 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___lsb 4 -#define reg_iop_sap_out_rw_gen_gated___clk0_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___lsb 7 -#define reg_iop_sap_out_rw_gen_gated___clk1_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___lsb 9 -#define reg_iop_sap_out_rw_gen_gated___clk1_gate_src___width 2 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___lsb 11 -#define reg_iop_sap_out_rw_gen_gated___clk1_force_src___width 3 -#define reg_iop_sap_out_rw_gen_gated_offset 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___lsb 7 -#define reg_iop_sap_out_rw_bus___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___lsb 9 -#define reg_iop_sap_out_rw_bus___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___lsb 11 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte1_gated_clk___bit 11 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___lsb 12 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte1_clk_inv___bit 12 -#define reg_iop_sap_out_rw_bus___byte1_delay___lsb 13 -#define reg_iop_sap_out_rw_bus___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte1_delay___bit 13 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___lsb 14 -#define reg_iop_sap_out_rw_bus___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___lsb 16 -#define reg_iop_sap_out_rw_bus___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___lsb 18 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte2_gated_clk___bit 18 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___lsb 19 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte2_clk_inv___bit 19 -#define reg_iop_sap_out_rw_bus___byte2_delay___lsb 20 -#define reg_iop_sap_out_rw_bus___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte2_delay___bit 20 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___lsb 21 -#define reg_iop_sap_out_rw_bus___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___lsb 23 -#define reg_iop_sap_out_rw_bus___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___lsb 25 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus___byte3_gated_clk___bit 25 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___lsb 26 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus___byte3_clk_inv___bit 26 -#define reg_iop_sap_out_rw_bus___byte3_delay___lsb 27 -#define reg_iop_sap_out_rw_bus___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus___byte3_delay___bit 27 -#define reg_iop_sap_out_rw_bus_offset 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_delay___bit 6 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_lo_oe___byte0_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___width 1 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_delay___bit 17 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_lo_oe___byte1_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_lo_oe_offset 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___lsb 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___lsb 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_gated_clk___bit 4 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___lsb 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_clk_inv___bit 5 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___lsb 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_delay___bit 6 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___lsb 7 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___lsb 9 -#define reg_iop_sap_out_rw_bus_hi_oe___byte2_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___lsb 11 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_sel___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___lsb 13 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_ext___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___lsb 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_gated_clk___bit 15 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___lsb 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_clk_inv___bit 16 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___lsb 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___width 1 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_delay___bit 17 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___lsb 18 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___lsb 20 -#define reg_iop_sap_out_rw_bus_hi_oe___byte3_logic_src___width 2 -#define reg_iop_sap_out_rw_bus_hi_oe_offset 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -#define reg_iop_sap_out_rw_gio___out_clk_sel___lsb 0 -#define reg_iop_sap_out_rw_gio___out_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___lsb 3 -#define reg_iop_sap_out_rw_gio___out_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___out_gated_clk___lsb 5 -#define reg_iop_sap_out_rw_gio___out_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___out_gated_clk___bit 5 -#define reg_iop_sap_out_rw_gio___out_clk_inv___lsb 6 -#define reg_iop_sap_out_rw_gio___out_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___out_clk_inv___bit 6 -#define reg_iop_sap_out_rw_gio___out_delay___lsb 7 -#define reg_iop_sap_out_rw_gio___out_delay___width 1 -#define reg_iop_sap_out_rw_gio___out_delay___bit 7 -#define reg_iop_sap_out_rw_gio___out_logic___lsb 8 -#define reg_iop_sap_out_rw_gio___out_logic___width 2 -#define reg_iop_sap_out_rw_gio___out_logic_src___lsb 10 -#define reg_iop_sap_out_rw_gio___out_logic_src___width 2 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___lsb 12 -#define reg_iop_sap_out_rw_gio___oe_clk_sel___width 3 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___lsb 15 -#define reg_iop_sap_out_rw_gio___oe_clk_ext___width 2 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___lsb 17 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___width 1 -#define reg_iop_sap_out_rw_gio___oe_gated_clk___bit 17 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___lsb 18 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___width 1 -#define reg_iop_sap_out_rw_gio___oe_clk_inv___bit 18 -#define reg_iop_sap_out_rw_gio___oe_delay___lsb 19 -#define reg_iop_sap_out_rw_gio___oe_delay___width 1 -#define reg_iop_sap_out_rw_gio___oe_delay___bit 19 -#define reg_iop_sap_out_rw_gio___oe_logic___lsb 20 -#define reg_iop_sap_out_rw_gio___oe_logic___width 2 -#define reg_iop_sap_out_rw_gio___oe_logic_src___lsb 22 -#define reg_iop_sap_out_rw_gio___oe_logic_src___width 2 -#define reg_iop_sap_out_rw_gio_offset 16 - - -/* Constants */ -#define regk_iop_sap_out_always 0x00000001 -#define regk_iop_sap_out_and 0x00000002 -#define regk_iop_sap_out_clk0 0x00000000 -#define regk_iop_sap_out_clk1 0x00000001 -#define regk_iop_sap_out_clk12 0x00000004 -#define regk_iop_sap_out_clk200 0x00000000 -#define regk_iop_sap_out_ext 0x00000002 -#define regk_iop_sap_out_gated 0x00000003 -#define regk_iop_sap_out_gio0 0x00000000 -#define regk_iop_sap_out_gio1 0x00000000 -#define regk_iop_sap_out_gio16 0x00000002 -#define regk_iop_sap_out_gio17 0x00000002 -#define regk_iop_sap_out_gio24 0x00000003 -#define regk_iop_sap_out_gio25 0x00000003 -#define regk_iop_sap_out_gio8 0x00000001 -#define regk_iop_sap_out_gio9 0x00000001 -#define regk_iop_sap_out_gio_out10 0x00000005 -#define regk_iop_sap_out_gio_out18 0x00000006 -#define regk_iop_sap_out_gio_out2 0x00000004 -#define regk_iop_sap_out_gio_out26 0x00000007 -#define regk_iop_sap_out_inv 0x00000001 -#define regk_iop_sap_out_nand 0x00000003 -#define regk_iop_sap_out_no 0x00000000 -#define regk_iop_sap_out_none 0x00000000 -#define regk_iop_sap_out_one 0x00000001 -#define regk_iop_sap_out_rw_bus_default 0x00000000 -#define regk_iop_sap_out_rw_bus_hi_oe_default 0x00000000 -#define regk_iop_sap_out_rw_bus_lo_oe_default 0x00000000 -#define regk_iop_sap_out_rw_gen_gated_default 0x00000000 -#define regk_iop_sap_out_rw_gio_default 0x00000000 -#define regk_iop_sap_out_rw_gio_size 0x00000020 -#define regk_iop_sap_out_spu_gio6 0x00000002 -#define regk_iop_sap_out_spu_gio7 0x00000003 -#define regk_iop_sap_out_timer_grp0_tmr2 0x00000000 -#define regk_iop_sap_out_timer_grp0_tmr3 0x00000001 -#define regk_iop_sap_out_timer_grp1_tmr2 0x00000002 -#define regk_iop_sap_out_timer_grp1_tmr3 0x00000003 -#define regk_iop_sap_out_tmr200 0x00000001 -#define regk_iop_sap_out_yes 0x00000001 -#endif /* __iop_sap_out_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h deleted file mode 100644 index c4b8bc386cb6..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cfg_defs_asm.h +++ /dev/null @@ -1,740 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cfg_defs_asm_h -#define __iop_sw_cfg_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cfg_defs_asm.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_crc_par_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_crc_par_owner_offset 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_in_owner_offset 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_dmc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_dmc_out_owner_offset 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_owner_offset 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_in_extra_owner_offset 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_owner_offset 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_fifo_out_extra_owner_offset 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_in_owner_offset 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_sap_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_sap_out_owner_offset 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_in_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_in_owner_offset 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_scrc_out_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_scrc_out_owner_offset 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___width 1 -#define reg_iop_sw_cfg_rw_spu_owner___cfg___bit 0 -#define reg_iop_sw_cfg_rw_spu_owner_offset 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_owner_offset 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_owner_offset 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp0_owner_offset 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp1_owner_offset 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp2_owner_offset 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp3_owner_offset 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp4_owner_offset 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp5_owner_offset 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp6_owner_offset 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner___cfg___width 2 -#define reg_iop_sw_cfg_rw_trigger_grp7_owner_offset 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_mask___byte0___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___lsb 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte1___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___lsb 16 -#define reg_iop_sw_cfg_rw_bus_mask___byte2___width 8 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___lsb 24 -#define reg_iop_sw_cfg_rw_bus_mask___byte3___width 8 -#define reg_iop_sw_cfg_rw_bus_mask_offset 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___lsb 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte0___bit 0 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___lsb 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte1___bit 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___lsb 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte2___bit 2 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___lsb 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___width 1 -#define reg_iop_sw_cfg_rw_bus_oe_mask___byte3___bit 3 -#define reg_iop_sw_cfg_rw_bus_oe_mask_offset 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_mask_offset 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___lsb 0 -#define reg_iop_sw_cfg_rw_gio_oe_mask___val___width 32 -#define reg_iop_sw_cfg_rw_gio_oe_mask_offset 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___lsb 0 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___lsb 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte1___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___lsb 4 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte2___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___lsb 6 -#define reg_iop_sw_cfg_rw_pinmapping___bus_byte3___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___lsb 8 -#define reg_iop_sw_cfg_rw_pinmapping___gio3_0___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___lsb 10 -#define reg_iop_sw_cfg_rw_pinmapping___gio7_4___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___lsb 12 -#define reg_iop_sw_cfg_rw_pinmapping___gio11_8___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___lsb 14 -#define reg_iop_sw_cfg_rw_pinmapping___gio15_12___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___lsb 16 -#define reg_iop_sw_cfg_rw_pinmapping___gio19_16___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___lsb 18 -#define reg_iop_sw_cfg_rw_pinmapping___gio23_20___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___lsb 20 -#define reg_iop_sw_cfg_rw_pinmapping___gio27_24___width 2 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___lsb 22 -#define reg_iop_sw_cfg_rw_pinmapping___gio31_28___width 2 -#define reg_iop_sw_cfg_rw_pinmapping_offset 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___lsb 0 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___lsb 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___lsb 4 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_lo_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___lsb 6 -#define reg_iop_sw_cfg_rw_bus_out_cfg___bus_hi_oe___width 2 -#define reg_iop_sw_cfg_rw_bus_out_cfg_offset 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio0_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio1_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio2_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg___gio3_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp0_cfg_offset 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio4_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio5_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio6_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg___gio7_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp1_cfg_offset 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio8_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio9_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio10_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg___gio11_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp2_cfg_offset 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio12_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio13_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio14_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg___gio15_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp3_cfg_offset 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio16_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio17_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio18_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg___gio19_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp4_cfg_offset 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio20_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio21_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio22_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg___gio23_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp5_cfg_offset 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio24_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio25_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio26_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg___gio27_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp6_cfg_offset 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___lsb 0 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___lsb 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio28_oe___bit 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___lsb 4 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___lsb 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio29_oe___bit 7 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___lsb 8 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___lsb 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio30_oe___bit 11 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___lsb 12 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31___width 3 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___lsb 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___width 1 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg___gio31_oe___bit 15 -#define reg_iop_sw_cfg_rw_gio_out_grp7_cfg_offset 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___lsb 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus0_in___bit 0 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___lsb 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___width 1 -#define reg_iop_sw_cfg_rw_spu_cfg___bus1_in___bit 1 -#define reg_iop_sw_cfg_rw_spu_cfg_offset 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp0_cfg_offset 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___lsb 0 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___ext_clk___width 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___lsb 3 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___lsb 5 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___lsb 7 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___lsb 9 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_en___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___lsb 11 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr0_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___lsb 13 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr1_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___lsb 15 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr2_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___lsb 17 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg___tmr3_dis___width 2 -#define reg_iop_sw_cfg_rw_timer_grp1_cfg_offset 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___lsb 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_dis___bit 0 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___lsb 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp0_en___bit 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___lsb 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_dis___bit 2 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___lsb 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp1_en___bit 3 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___lsb 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_dis___bit 4 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___lsb 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp2_en___bit 5 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___lsb 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_dis___bit 6 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___lsb 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp3_en___bit 7 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___lsb 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_dis___bit 8 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___lsb 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp4_en___bit 9 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___lsb 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_dis___bit 10 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___lsb 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp5_en___bit 11 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___lsb 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_dis___bit 12 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___lsb 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp6_en___bit 13 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___lsb 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_dis___bit 14 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___lsb 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___width 1 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg___grp7_en___bit 15 -#define reg_iop_sw_cfg_rw_trigger_grps_cfg_offset 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_pdp_cfg___out_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___lsb 4 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_src___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___lsb 6 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_size___width 3 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___lsb 9 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_last___width 2 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___lsb 11 -#define reg_iop_sw_cfg_rw_pdp_cfg___in_strb___width 4 -#define reg_iop_sw_cfg_rw_pdp_cfg_offset 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___lsb 0 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_out_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___lsb 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_data___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___lsb 6 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_last___width 2 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___lsb 8 -#define reg_iop_sw_cfg_rw_sdp_cfg___sdp_in_strb___width 3 -#define reg_iop_sw_cfg_rw_sdp_cfg_offset 164 - - -/* Constants */ -#define regk_iop_sw_cfg_a 0x00000001 -#define regk_iop_sw_cfg_b 0x00000002 -#define regk_iop_sw_cfg_bus 0x00000000 -#define regk_iop_sw_cfg_bus_rot16 0x00000002 -#define regk_iop_sw_cfg_bus_rot24 0x00000003 -#define regk_iop_sw_cfg_bus_rot8 0x00000001 -#define regk_iop_sw_cfg_clk12 0x00000000 -#define regk_iop_sw_cfg_cpu 0x00000000 -#define regk_iop_sw_cfg_gated_clk0 0x0000000e -#define regk_iop_sw_cfg_gated_clk1 0x0000000f -#define regk_iop_sw_cfg_gio0 0x00000004 -#define regk_iop_sw_cfg_gio1 0x00000001 -#define regk_iop_sw_cfg_gio2 0x00000005 -#define regk_iop_sw_cfg_gio3 0x00000002 -#define regk_iop_sw_cfg_gio4 0x00000006 -#define regk_iop_sw_cfg_gio5 0x00000003 -#define regk_iop_sw_cfg_gio6 0x00000007 -#define regk_iop_sw_cfg_gio7 0x00000004 -#define regk_iop_sw_cfg_gio_in18 0x00000002 -#define regk_iop_sw_cfg_gio_in19 0x00000003 -#define regk_iop_sw_cfg_gio_in20 0x00000004 -#define regk_iop_sw_cfg_gio_in21 0x00000005 -#define regk_iop_sw_cfg_gio_in26 0x00000006 -#define regk_iop_sw_cfg_gio_in27 0x00000007 -#define regk_iop_sw_cfg_gio_in4 0x00000000 -#define regk_iop_sw_cfg_gio_in5 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp0_tmr2 0x00000001 -#define regk_iop_sw_cfg_last_timer_grp1_tmr2 0x00000002 -#define regk_iop_sw_cfg_last_timer_grp1_tmr3 0x00000003 -#define regk_iop_sw_cfg_mpu 0x00000001 -#define regk_iop_sw_cfg_none 0x00000000 -#define regk_iop_sw_cfg_pdp_out 0x00000001 -#define regk_iop_sw_cfg_pdp_out_hi 0x00000001 -#define regk_iop_sw_cfg_pdp_out_lo 0x00000000 -#define regk_iop_sw_cfg_rw_bus_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_bus_out_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_crc_par_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_dmc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_extra_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_fifo_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_oe_mask_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_pinmapping_default 0x00555555 -#define regk_iop_sw_cfg_rw_sap_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sap_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_in_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_scrc_out_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_sdp_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_spu_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_cfg_default 0x00000000 -#define regk_iop_sw_cfg_rw_timer_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp0_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp1_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp2_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp3_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp4_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp5_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp6_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grp7_owner_default 0x00000000 -#define regk_iop_sw_cfg_rw_trigger_grps_cfg_default 0x00000000 -#define regk_iop_sw_cfg_sdp_out 0x00000004 -#define regk_iop_sw_cfg_size16 0x00000002 -#define regk_iop_sw_cfg_size24 0x00000003 -#define regk_iop_sw_cfg_size32 0x00000004 -#define regk_iop_sw_cfg_size8 0x00000001 -#define regk_iop_sw_cfg_spu 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_hi 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out0_lo 0x00000002 -#define regk_iop_sw_cfg_spu_bus_out1_hi 0x00000003 -#define regk_iop_sw_cfg_spu_bus_out1_lo 0x00000003 -#define regk_iop_sw_cfg_spu_g0 0x00000007 -#define regk_iop_sw_cfg_spu_g1 0x00000007 -#define regk_iop_sw_cfg_spu_g2 0x00000007 -#define regk_iop_sw_cfg_spu_g3 0x00000007 -#define regk_iop_sw_cfg_spu_g4 0x00000007 -#define regk_iop_sw_cfg_spu_g5 0x00000007 -#define regk_iop_sw_cfg_spu_g6 0x00000007 -#define regk_iop_sw_cfg_spu_g7 0x00000007 -#define regk_iop_sw_cfg_spu_gio0 0x00000000 -#define regk_iop_sw_cfg_spu_gio1 0x00000001 -#define regk_iop_sw_cfg_spu_gio5 0x00000005 -#define regk_iop_sw_cfg_spu_gio6 0x00000006 -#define regk_iop_sw_cfg_spu_gio7 0x00000007 -#define regk_iop_sw_cfg_spu_gio_out0 0x00000008 -#define regk_iop_sw_cfg_spu_gio_out1 0x00000009 -#define regk_iop_sw_cfg_spu_gio_out2 0x0000000a -#define regk_iop_sw_cfg_spu_gio_out3 0x0000000b -#define regk_iop_sw_cfg_spu_gio_out4 0x0000000c -#define regk_iop_sw_cfg_spu_gio_out5 0x0000000d -#define regk_iop_sw_cfg_spu_gio_out6 0x0000000e -#define regk_iop_sw_cfg_spu_gio_out7 0x0000000f -#define regk_iop_sw_cfg_spu_gioout0 0x00000000 -#define regk_iop_sw_cfg_spu_gioout1 0x00000000 -#define regk_iop_sw_cfg_spu_gioout10 0x00000007 -#define regk_iop_sw_cfg_spu_gioout11 0x00000007 -#define regk_iop_sw_cfg_spu_gioout12 0x00000007 -#define regk_iop_sw_cfg_spu_gioout13 0x00000007 -#define regk_iop_sw_cfg_spu_gioout14 0x00000007 -#define regk_iop_sw_cfg_spu_gioout15 0x00000007 -#define regk_iop_sw_cfg_spu_gioout16 0x00000007 -#define regk_iop_sw_cfg_spu_gioout17 0x00000007 -#define regk_iop_sw_cfg_spu_gioout18 0x00000007 -#define regk_iop_sw_cfg_spu_gioout19 0x00000007 -#define regk_iop_sw_cfg_spu_gioout2 0x00000001 -#define regk_iop_sw_cfg_spu_gioout20 0x00000007 -#define regk_iop_sw_cfg_spu_gioout21 0x00000007 -#define regk_iop_sw_cfg_spu_gioout22 0x00000007 -#define regk_iop_sw_cfg_spu_gioout23 0x00000007 -#define regk_iop_sw_cfg_spu_gioout24 0x00000007 -#define regk_iop_sw_cfg_spu_gioout25 0x00000007 -#define regk_iop_sw_cfg_spu_gioout26 0x00000007 -#define regk_iop_sw_cfg_spu_gioout27 0x00000007 -#define regk_iop_sw_cfg_spu_gioout28 0x00000007 -#define regk_iop_sw_cfg_spu_gioout29 0x00000007 -#define regk_iop_sw_cfg_spu_gioout3 0x00000001 -#define regk_iop_sw_cfg_spu_gioout30 0x00000007 -#define regk_iop_sw_cfg_spu_gioout31 0x00000007 -#define regk_iop_sw_cfg_spu_gioout4 0x00000002 -#define regk_iop_sw_cfg_spu_gioout5 0x00000002 -#define regk_iop_sw_cfg_spu_gioout6 0x00000003 -#define regk_iop_sw_cfg_spu_gioout7 0x00000003 -#define regk_iop_sw_cfg_spu_gioout8 0x00000007 -#define regk_iop_sw_cfg_spu_gioout9 0x00000007 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr0 0x00000001 -#define regk_iop_sw_cfg_strb_timer_grp0_tmr1 0x00000002 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_strb_timer_grp1_tmr1 0x00000002 -#define regk_iop_sw_cfg_timer_grp0 0x00000000 -#define regk_iop_sw_cfg_timer_grp0_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp0_strb0 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb1 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb2 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_strb3 0x00000005 -#define regk_iop_sw_cfg_timer_grp0_tmr0 0x00000002 -#define regk_iop_sw_cfg_timer_grp1 0x00000000 -#define regk_iop_sw_cfg_timer_grp1_rot 0x00000001 -#define regk_iop_sw_cfg_timer_grp1_strb0 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb1 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb2 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_strb3 0x00000006 -#define regk_iop_sw_cfg_timer_grp1_tmr0 0x00000003 -#define regk_iop_sw_cfg_trig0_0 0x00000000 -#define regk_iop_sw_cfg_trig0_1 0x00000000 -#define regk_iop_sw_cfg_trig0_2 0x00000000 -#define regk_iop_sw_cfg_trig0_3 0x00000000 -#define regk_iop_sw_cfg_trig1_0 0x00000000 -#define regk_iop_sw_cfg_trig1_1 0x00000000 -#define regk_iop_sw_cfg_trig1_2 0x00000000 -#define regk_iop_sw_cfg_trig1_3 0x00000000 -#define regk_iop_sw_cfg_trig2_0 0x00000001 -#define regk_iop_sw_cfg_trig2_1 0x00000001 -#define regk_iop_sw_cfg_trig2_2 0x00000001 -#define regk_iop_sw_cfg_trig2_3 0x00000001 -#define regk_iop_sw_cfg_trig3_0 0x00000001 -#define regk_iop_sw_cfg_trig3_1 0x00000001 -#define regk_iop_sw_cfg_trig3_2 0x00000001 -#define regk_iop_sw_cfg_trig3_3 0x00000001 -#define regk_iop_sw_cfg_trig4_0 0x00000002 -#define regk_iop_sw_cfg_trig4_1 0x00000002 -#define regk_iop_sw_cfg_trig4_2 0x00000002 -#define regk_iop_sw_cfg_trig4_3 0x00000002 -#define regk_iop_sw_cfg_trig5_0 0x00000002 -#define regk_iop_sw_cfg_trig5_1 0x00000002 -#define regk_iop_sw_cfg_trig5_2 0x00000002 -#define regk_iop_sw_cfg_trig5_3 0x00000002 -#define regk_iop_sw_cfg_trig6_0 0x00000003 -#define regk_iop_sw_cfg_trig6_1 0x00000003 -#define regk_iop_sw_cfg_trig6_2 0x00000003 -#define regk_iop_sw_cfg_trig6_3 0x00000003 -#define regk_iop_sw_cfg_trig7_0 0x00000003 -#define regk_iop_sw_cfg_trig7_1 0x00000003 -#define regk_iop_sw_cfg_trig7_2 0x00000003 -#define regk_iop_sw_cfg_trig7_3 0x00000003 -#endif /* __iop_sw_cfg_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h deleted file mode 100644 index 89f36dc1f96d..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_cpu_defs_asm.h +++ /dev/null @@ -1,951 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cpu_defs_asm_h -#define __iop_sw_cpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_cpu_defs_asm.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mpu_trace_offset 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_cpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_cpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_cpu_rw_mc_data___val___width 32 -#define reg_iop_sw_cpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -#define reg_iop_sw_cpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_cpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_cpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_cpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_cpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_cpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_cpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_gio_in_offset 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___width 1 -#define reg_iop_sw_cpu_rw_intr0_mask___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_intr0_mask_offset 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_rw_ack_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_rw_ack_intr0_offset 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_intr0_offset 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_0___bit 0 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_1___bit 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_2___bit 2 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_3___bit 3 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_4___bit 4 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_5___bit 5 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_6___bit 6 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_7___bit 7 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_8___bit 8 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_9___bit 9 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_10___bit 10 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_11___bit 11 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_12___bit 12 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_13___bit 13 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_14___bit 14 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___mpu_15___bit 15 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_0___bit 16 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_1___bit 17 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_2___bit 18 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_3___bit 19 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_4___bit 20 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_5___bit 21 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_6___bit 22 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_7___bit 23 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_8___bit 24 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_9___bit 25 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_10___bit 26 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_11___bit 27 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_12___bit 28 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_13___bit 29 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_14___bit 30 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___width 1 -#define reg_iop_sw_cpu_r_masked_intr0___spu_15___bit 31 -#define reg_iop_sw_cpu_r_masked_intr0_offset 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___lsb 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_in___bit 16 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___lsb 17 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___dmc_out___bit 17 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___lsb 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in___bit 18 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___lsb 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out___bit 19 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp0___bit 30 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___width 1 -#define reg_iop_sw_cpu_rw_intr1_mask___timer_grp1___bit 31 -#define reg_iop_sw_cpu_rw_intr1_mask_offset 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_rw_ack_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_rw_ack_intr1_offset 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_intr1_offset 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___lsb 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_16___bit 0 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___lsb 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_17___bit 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___lsb 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_18___bit 2 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___lsb 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_19___bit 3 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___lsb 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_20___bit 4 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___lsb 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_21___bit 5 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___lsb 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_22___bit 6 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___lsb 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_23___bit 7 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___lsb 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_24___bit 8 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___lsb 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_25___bit 9 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___lsb 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_26___bit 10 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___lsb 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_27___bit 11 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___lsb 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_28___bit 12 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___lsb 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_29___bit 13 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___lsb 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_30___bit 14 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___lsb 15 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___mpu_31___bit 15 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___lsb 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_in___bit 16 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___lsb 17 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___dmc_out___bit 17 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___lsb 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in___bit 18 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___lsb 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out___bit 19 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___lsb 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_in_extra___bit 20 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___lsb 21 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___fifo_out_extra___bit 21 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___lsb 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp0___bit 22 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___lsb 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp1___bit 23 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___lsb 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp2___bit 24 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___lsb 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp3___bit 25 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___lsb 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp4___bit 26 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___lsb 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp5___bit 27 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___lsb 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp6___bit 28 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___lsb 29 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___trigger_grp7___bit 29 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___lsb 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp0___bit 30 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___lsb 31 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___width 1 -#define reg_iop_sw_cpu_r_masked_intr1___timer_grp1___bit 31 -#define reg_iop_sw_cpu_r_masked_intr1_offset 104 - - -/* Constants */ -#define regk_iop_sw_cpu_copy 0x00000000 -#define regk_iop_sw_cpu_no 0x00000000 -#define regk_iop_sw_cpu_rd 0x00000002 -#define regk_iop_sw_cpu_reg_copy 0x00000001 -#define regk_iop_sw_cpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr0_mask_default 0x00000000 -#define regk_iop_sw_cpu_rw_intr1_mask_default 0x00000000 -#define regk_iop_sw_cpu_wr 0x00000003 -#define regk_iop_sw_cpu_yes 0x00000001 -#endif /* __iop_sw_cpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h deleted file mode 100644 index 45e19d79dba9..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_mpu_defs_asm.h +++ /dev/null @@ -1,1087 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_mpu_defs_asm_h -#define __iop_sw_mpu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_mpu_defs_asm.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___lsb 0 -#define reg_iop_sw_mpu_rw_sw_cfg_owner___cfg___width 2 -#define reg_iop_sw_mpu_rw_sw_cfg_owner_offset 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_trace_offset 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_spu_fsm_trace_offset 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_mpu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_mpu_rw_mc_ctrl_offset 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_mpu_rw_mc_data___val___width 32 -#define reg_iop_sw_mpu_rw_mc_data_offset 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_mc_addr_offset 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -#define reg_iop_sw_mpu_rs_mc_data_offset 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_data_offset 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_mpu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_mpu_r_mc_stat_offset 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_clr_mask_offset 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_mpu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_mpu_rw_bus_set_mask_offset 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_clr_mask_offset 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_mpu_rw_bus_oe_set_mask_offset 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_bus_in_offset 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_clr_mask_offset 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_set_mask_offset 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_clr_mask_offset 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_mpu_rw_gio_oe_set_mask_offset 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_gio_in_offset 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_rw_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_rw_cpu_intr_offset 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___lsb 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr16___bit 16 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___lsb 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr17___bit 17 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___lsb 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr18___bit 18 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___lsb 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr19___bit 19 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___lsb 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr20___bit 20 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___lsb 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr21___bit 21 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___lsb 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr22___bit 22 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___lsb 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr23___bit 23 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___lsb 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr24___bit 24 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___lsb 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr25___bit 25 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___lsb 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr26___bit 26 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___lsb 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr27___bit 27 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___lsb 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr28___bit 28 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___lsb 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr29___bit 29 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___lsb 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr30___bit 30 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___lsb 31 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___width 1 -#define reg_iop_sw_mpu_r_cpu_intr___intr31___bit 31 -#define reg_iop_sw_mpu_r_cpu_intr_offset 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp0_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp0_mask_offset 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp0_offset 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp0_offset 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr0___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr1___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr2___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___spu_intr3___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp0___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp0_offset 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp1_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp1_mask_offset 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp1_offset 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp1_offset 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr4___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr5___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr6___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___spu_intr7___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp1___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp1_offset 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp0___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___timer_grp1___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp2_mask___dmc_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp2_mask_offset 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp2_offset 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp2_offset 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr8___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp0___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp0___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr9___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp1___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___timer_grp1___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr10___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp2___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_out_extra___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___spu_intr11___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___trigger_grp3___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___fifo_in_extra___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp2___dmc_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp2_offset 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___lsb 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_out___bit 3 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___lsb 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___dmc_in___bit 7 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp0___bit 10 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___lsb 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_out___bit 11 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___timer_grp1___bit 14 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___lsb 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___width 1 -#define reg_iop_sw_mpu_rw_intr_grp3_mask___fifo_in___bit 15 -#define reg_iop_sw_mpu_rw_intr_grp3_mask_offset 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_rw_ack_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_rw_ack_intr_grp3_offset 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_intr_grp3_offset 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___lsb 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr12___bit 0 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___lsb 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp4___bit 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___lsb 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out_extra___bit 2 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___lsb 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_out___bit 3 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___lsb 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr13___bit 4 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___lsb 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp5___bit 5 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___lsb 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in_extra___bit 6 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___lsb 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___dmc_in___bit 7 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___lsb 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr14___bit 8 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___lsb 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp6___bit 9 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___lsb 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp0___bit 10 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___lsb 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_out___bit 11 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___lsb 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___spu_intr15___bit 12 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___lsb 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___trigger_grp7___bit 13 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___lsb 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___timer_grp1___bit 14 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___lsb 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___width 1 -#define reg_iop_sw_mpu_r_masked_intr_grp3___fifo_in___bit 15 -#define reg_iop_sw_mpu_r_masked_intr_grp3_offset 144 - - -/* Constants */ -#define regk_iop_sw_mpu_copy 0x00000000 -#define regk_iop_sw_mpu_cpu 0x00000000 -#define regk_iop_sw_mpu_mpu 0x00000001 -#define regk_iop_sw_mpu_no 0x00000000 -#define regk_iop_sw_mpu_nop 0x00000000 -#define regk_iop_sw_mpu_rd 0x00000002 -#define regk_iop_sw_mpu_reg_copy 0x00000001 -#define regk_iop_sw_mpu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp0_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp1_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp2_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_intr_grp3_mask_default 0x00000000 -#define regk_iop_sw_mpu_rw_sw_cfg_owner_default 0x00000000 -#define regk_iop_sw_mpu_set 0x00000001 -#define regk_iop_sw_mpu_spu 0x00000002 -#define regk_iop_sw_mpu_wr 0x00000003 -#define regk_iop_sw_mpu_yes 0x00000001 -#endif /* __iop_sw_mpu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h deleted file mode 100644 index 55afb6e320e4..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_sw_spu_defs_asm.h +++ /dev/null @@ -1,524 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_spu_defs_asm_h -#define __iop_sw_spu_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_sw_spu_defs_asm.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_trace_offset 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___lsb 0 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___keep_owner___bit 0 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___lsb 1 -#define reg_iop_sw_spu_rw_mc_ctrl___cmd___width 2 -#define reg_iop_sw_spu_rw_mc_ctrl___size___lsb 3 -#define reg_iop_sw_spu_rw_mc_ctrl___size___width 3 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___lsb 6 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___width 1 -#define reg_iop_sw_spu_rw_mc_ctrl___wr_spu_mem___bit 6 -#define reg_iop_sw_spu_rw_mc_ctrl_offset 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_data___val___lsb 0 -#define reg_iop_sw_spu_rw_mc_data___val___width 32 -#define reg_iop_sw_spu_rw_mc_data_offset 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mc_addr_offset 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -#define reg_iop_sw_spu_rs_mc_data_offset 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_data_offset 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___lsb 0 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_cpu___bit 0 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___lsb 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_mpu___bit 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___lsb 2 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___busy_spu___bit 2 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___lsb 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_cpu___bit 3 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___lsb 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_mpu___bit 4 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___lsb 5 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___width 1 -#define reg_iop_sw_spu_r_mc_stat___owned_by_spu___bit 5 -#define reg_iop_sw_spu_r_mc_stat_offset 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_clr_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_offset 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___lsb 16 -#define reg_iop_sw_spu_rw_bus_set_mask___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___lsb 24 -#define reg_iop_sw_spu_rw_bus_set_mask___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_offset 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_clr_mask_offset 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte0___bit 0 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___lsb 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte1___bit 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___lsb 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte2___bit 2 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___lsb 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___width 1 -#define reg_iop_sw_spu_rw_bus_oe_set_mask___byte3___bit 3 -#define reg_iop_sw_spu_rw_bus_oe_set_mask_offset 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_bus_in_offset 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_clr_mask_offset 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_set_mask_offset 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_offset 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask___val___width 32 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_offset 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_gio_in_offset 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_lo_offset 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_clr_mask_hi_offset 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte0___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo___byte1___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_lo_offset 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___lsb 0 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte2___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___lsb 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi___byte3___width 8 -#define reg_iop_sw_spu_rw_bus_set_mask_hi_offset 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_lo_offset 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_clr_mask_hi_offset 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_lo_offset 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_set_mask_hi_offset 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_lo_offset 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_clr_mask_hi_offset 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_lo_offset 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___lsb 0 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi___val___width 16 -#define reg_iop_sw_spu_rw_gio_oe_set_mask_hi_offset 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_cpu_intr_offset 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_cpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_cpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_cpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_cpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_cpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_cpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_cpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_cpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_cpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_cpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_cpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_cpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_cpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_cpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_cpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_cpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_cpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_cpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_cpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_cpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_cpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_cpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_cpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_cpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_cpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_cpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_cpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_cpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_cpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_cpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_cpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_cpu_intr_offset 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___lsb 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp0___bit 0 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___lsb 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp1___bit 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___lsb 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp2___bit 2 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___lsb 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp3___bit 3 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___lsb 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp4___bit 4 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___lsb 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp5___bit 5 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___lsb 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp6___bit 6 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___lsb 7 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___width 1 -#define reg_iop_sw_spu_r_hw_intr___trigger_grp7___bit 7 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___lsb 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp0___bit 8 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___lsb 9 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___width 1 -#define reg_iop_sw_spu_r_hw_intr___timer_grp1___bit 9 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___lsb 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out___bit 10 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___lsb 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_out_extra___bit 11 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___lsb 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in___bit 12 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___lsb 13 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___width 1 -#define reg_iop_sw_spu_r_hw_intr___fifo_in_extra___bit 13 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___lsb 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_out___bit 14 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___lsb 15 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___width 1 -#define reg_iop_sw_spu_r_hw_intr___dmc_in___bit 15 -#define reg_iop_sw_spu_r_hw_intr_offset 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -#define reg_iop_sw_spu_rw_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_rw_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_rw_mpu_intr_offset 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -#define reg_iop_sw_spu_r_mpu_intr___intr0___lsb 0 -#define reg_iop_sw_spu_r_mpu_intr___intr0___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr0___bit 0 -#define reg_iop_sw_spu_r_mpu_intr___intr1___lsb 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr1___bit 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___lsb 2 -#define reg_iop_sw_spu_r_mpu_intr___intr2___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr2___bit 2 -#define reg_iop_sw_spu_r_mpu_intr___intr3___lsb 3 -#define reg_iop_sw_spu_r_mpu_intr___intr3___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr3___bit 3 -#define reg_iop_sw_spu_r_mpu_intr___intr4___lsb 4 -#define reg_iop_sw_spu_r_mpu_intr___intr4___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr4___bit 4 -#define reg_iop_sw_spu_r_mpu_intr___intr5___lsb 5 -#define reg_iop_sw_spu_r_mpu_intr___intr5___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr5___bit 5 -#define reg_iop_sw_spu_r_mpu_intr___intr6___lsb 6 -#define reg_iop_sw_spu_r_mpu_intr___intr6___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr6___bit 6 -#define reg_iop_sw_spu_r_mpu_intr___intr7___lsb 7 -#define reg_iop_sw_spu_r_mpu_intr___intr7___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr7___bit 7 -#define reg_iop_sw_spu_r_mpu_intr___intr8___lsb 8 -#define reg_iop_sw_spu_r_mpu_intr___intr8___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr8___bit 8 -#define reg_iop_sw_spu_r_mpu_intr___intr9___lsb 9 -#define reg_iop_sw_spu_r_mpu_intr___intr9___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr9___bit 9 -#define reg_iop_sw_spu_r_mpu_intr___intr10___lsb 10 -#define reg_iop_sw_spu_r_mpu_intr___intr10___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr10___bit 10 -#define reg_iop_sw_spu_r_mpu_intr___intr11___lsb 11 -#define reg_iop_sw_spu_r_mpu_intr___intr11___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr11___bit 11 -#define reg_iop_sw_spu_r_mpu_intr___intr12___lsb 12 -#define reg_iop_sw_spu_r_mpu_intr___intr12___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr12___bit 12 -#define reg_iop_sw_spu_r_mpu_intr___intr13___lsb 13 -#define reg_iop_sw_spu_r_mpu_intr___intr13___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr13___bit 13 -#define reg_iop_sw_spu_r_mpu_intr___intr14___lsb 14 -#define reg_iop_sw_spu_r_mpu_intr___intr14___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr14___bit 14 -#define reg_iop_sw_spu_r_mpu_intr___intr15___lsb 15 -#define reg_iop_sw_spu_r_mpu_intr___intr15___width 1 -#define reg_iop_sw_spu_r_mpu_intr___intr15___bit 15 -#define reg_iop_sw_spu_r_mpu_intr_offset 132 - - -/* Constants */ -#define regk_iop_sw_spu_copy 0x00000000 -#define regk_iop_sw_spu_no 0x00000000 -#define regk_iop_sw_spu_nop 0x00000000 -#define regk_iop_sw_spu_rd 0x00000002 -#define regk_iop_sw_spu_reg_copy 0x00000001 -#define regk_iop_sw_spu_rw_bus_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_bus_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_clr_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_oe_set_mask_default 0x00000000 -#define regk_iop_sw_spu_rw_gio_set_mask_default 0x00000000 -#define regk_iop_sw_spu_set 0x00000001 -#define regk_iop_sw_spu_wr 0x00000003 -#define regk_iop_sw_spu_yes 0x00000001 -#endif /* __iop_sw_spu_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h deleted file mode 100644 index 79ff8fafd3bf..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/asm/iop_version_defs_asm.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_version_defs_asm_h -#define __iop_version_defs_asm_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -asm -outfile iop_version_defs_asm.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_version, scope iop_version, type r */ -#define reg_iop_version_r_version___nr___lsb 0 -#define reg_iop_version_r_version___nr___width 8 -#define reg_iop_version_r_version_offset 0 - - -/* Constants */ -#define regk_iop_version_v2_0 0x00000002 -#endif /* __iop_version_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h deleted file mode 100644 index 23d731f36145..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_reg_space.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Autogenerated Changes here will be lost! - * generated by ./gen_sw.pl Wed Feb 14 09:27:48 2007 iop_sw.cfg - */ -#define regi_iop_version (regi_iop + 0) -#define regi_iop_fifo_in_extra (regi_iop + 64) -#define regi_iop_fifo_out_extra (regi_iop + 128) -#define regi_iop_trigger_grp0 (regi_iop + 192) -#define regi_iop_trigger_grp1 (regi_iop + 256) -#define regi_iop_trigger_grp2 (regi_iop + 320) -#define regi_iop_trigger_grp3 (regi_iop + 384) -#define regi_iop_trigger_grp4 (regi_iop + 448) -#define regi_iop_trigger_grp5 (regi_iop + 512) -#define regi_iop_trigger_grp6 (regi_iop + 576) -#define regi_iop_trigger_grp7 (regi_iop + 640) -#define regi_iop_crc_par (regi_iop + 768) -#define regi_iop_dmc_in (regi_iop + 896) -#define regi_iop_dmc_out (regi_iop + 1024) -#define regi_iop_fifo_in (regi_iop + 1152) -#define regi_iop_fifo_out (regi_iop + 1280) -#define regi_iop_scrc_in (regi_iop + 1408) -#define regi_iop_scrc_out (regi_iop + 1536) -#define regi_iop_timer_grp0 (regi_iop + 1664) -#define regi_iop_timer_grp1 (regi_iop + 1792) -#define regi_iop_sap_in (regi_iop + 2048) -#define regi_iop_sap_out (regi_iop + 2304) -#define regi_iop_spu (regi_iop + 2560) -#define regi_iop_sw_cfg (regi_iop + 2816) -#define regi_iop_sw_cpu (regi_iop + 3072) -#define regi_iop_sw_mpu (regi_iop + 3328) -#define regi_iop_sw_spu (regi_iop + 3584) -#define regi_iop_mpu (regi_iop + 4096) diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h deleted file mode 100644 index 1d6c09a3230d..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_in_defs.h +++ /dev/null @@ -1,142 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_in_defs_h -#define __iop_sap_in_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_in.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_in_defs.h iop_sap_in.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_in */ - -#define STRIDE_iop_sap_in_rw_bus_byte 4 -/* Register rw_bus_byte, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int dummy1 : 23; -} reg_iop_sap_in_rw_bus_byte; -#define REG_RD_ADDR_iop_sap_in_rw_bus_byte 0 -#define REG_WR_ADDR_iop_sap_in_rw_bus_byte 0 - -#define STRIDE_iop_sap_in_rw_gio 4 -/* Register rw_gio, scope iop_sap_in, type rw */ -typedef struct { - unsigned int sync_sel : 2; - unsigned int sync_ext_src : 3; - unsigned int sync_edge : 2; - unsigned int delay : 2; - unsigned int logic : 2; - unsigned int dummy1 : 21; -} reg_iop_sap_in_rw_gio; -#define REG_RD_ADDR_iop_sap_in_rw_gio 16 -#define REG_WR_ADDR_iop_sap_in_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_in_and = 0x00000002, - regk_iop_sap_in_ext_clk200 = 0x00000003, - regk_iop_sap_in_gio0 = 0x00000000, - regk_iop_sap_in_gio12 = 0x00000003, - regk_iop_sap_in_gio16 = 0x00000004, - regk_iop_sap_in_gio20 = 0x00000005, - regk_iop_sap_in_gio24 = 0x00000006, - regk_iop_sap_in_gio28 = 0x00000007, - regk_iop_sap_in_gio4 = 0x00000001, - regk_iop_sap_in_gio8 = 0x00000002, - regk_iop_sap_in_inv = 0x00000001, - regk_iop_sap_in_neg = 0x00000002, - regk_iop_sap_in_no = 0x00000000, - regk_iop_sap_in_no_del_ext_clk200 = 0x00000002, - regk_iop_sap_in_none = 0x00000000, - regk_iop_sap_in_one = 0x00000001, - regk_iop_sap_in_or = 0x00000003, - regk_iop_sap_in_pos = 0x00000001, - regk_iop_sap_in_pos_neg = 0x00000003, - regk_iop_sap_in_rw_bus_byte_default = 0x00000000, - regk_iop_sap_in_rw_bus_byte_size = 0x00000004, - regk_iop_sap_in_rw_gio_default = 0x00000000, - regk_iop_sap_in_rw_gio_size = 0x00000020, - regk_iop_sap_in_timer_grp0_tmr3 = 0x00000000, - regk_iop_sap_in_timer_grp1_tmr3 = 0x00000001, - regk_iop_sap_in_tmr_clk200 = 0x00000001, - regk_iop_sap_in_two = 0x00000002, - regk_iop_sap_in_two_clk200 = 0x00000000 -}; -#endif /* __iop_sap_in_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h deleted file mode 100644 index 1cbd30efadb7..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sap_out_defs.h +++ /dev/null @@ -1,232 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sap_out_defs_h -#define __iop_sap_out_defs_h - -/* - * This file is autogenerated from - * file: iop_sap_out.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sap_out_defs.h iop_sap_out.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sap_out */ - -/* Register rw_gen_gated, scope iop_sap_out, type rw */ -typedef struct { - unsigned int clk0_src : 2; - unsigned int clk0_gate_src : 2; - unsigned int clk0_force_src : 3; - unsigned int clk1_src : 2; - unsigned int clk1_gate_src : 2; - unsigned int clk1_force_src : 3; - unsigned int dummy1 : 18; -} reg_iop_sap_out_rw_gen_gated; -#define REG_RD_ADDR_iop_sap_out_rw_gen_gated 0 -#define REG_WR_ADDR_iop_sap_out_rw_gen_gated 0 - -/* Register rw_bus, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int dummy1 : 4; -} reg_iop_sap_out_rw_bus; -#define REG_RD_ADDR_iop_sap_out_rw_bus 4 -#define REG_WR_ADDR_iop_sap_out_rw_bus 4 - -/* Register rw_bus_lo_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte0_clk_sel : 2; - unsigned int byte0_clk_ext : 2; - unsigned int byte0_gated_clk : 1; - unsigned int byte0_clk_inv : 1; - unsigned int byte0_delay : 1; - unsigned int byte0_logic : 2; - unsigned int byte0_logic_src : 2; - unsigned int byte1_clk_sel : 2; - unsigned int byte1_clk_ext : 2; - unsigned int byte1_gated_clk : 1; - unsigned int byte1_clk_inv : 1; - unsigned int byte1_delay : 1; - unsigned int byte1_logic : 2; - unsigned int byte1_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_lo_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_lo_oe 8 -#define REG_WR_ADDR_iop_sap_out_rw_bus_lo_oe 8 - -/* Register rw_bus_hi_oe, scope iop_sap_out, type rw */ -typedef struct { - unsigned int byte2_clk_sel : 2; - unsigned int byte2_clk_ext : 2; - unsigned int byte2_gated_clk : 1; - unsigned int byte2_clk_inv : 1; - unsigned int byte2_delay : 1; - unsigned int byte2_logic : 2; - unsigned int byte2_logic_src : 2; - unsigned int byte3_clk_sel : 2; - unsigned int byte3_clk_ext : 2; - unsigned int byte3_gated_clk : 1; - unsigned int byte3_clk_inv : 1; - unsigned int byte3_delay : 1; - unsigned int byte3_logic : 2; - unsigned int byte3_logic_src : 2; - unsigned int dummy1 : 10; -} reg_iop_sap_out_rw_bus_hi_oe; -#define REG_RD_ADDR_iop_sap_out_rw_bus_hi_oe 12 -#define REG_WR_ADDR_iop_sap_out_rw_bus_hi_oe 12 - -#define STRIDE_iop_sap_out_rw_gio 4 -/* Register rw_gio, scope iop_sap_out, type rw */ -typedef struct { - unsigned int out_clk_sel : 3; - unsigned int out_clk_ext : 2; - unsigned int out_gated_clk : 1; - unsigned int out_clk_inv : 1; - unsigned int out_delay : 1; - unsigned int out_logic : 2; - unsigned int out_logic_src : 2; - unsigned int oe_clk_sel : 3; - unsigned int oe_clk_ext : 2; - unsigned int oe_gated_clk : 1; - unsigned int oe_clk_inv : 1; - unsigned int oe_delay : 1; - unsigned int oe_logic : 2; - unsigned int oe_logic_src : 2; - unsigned int dummy1 : 8; -} reg_iop_sap_out_rw_gio; -#define REG_RD_ADDR_iop_sap_out_rw_gio 16 -#define REG_WR_ADDR_iop_sap_out_rw_gio 16 - - -/* Constants */ -enum { - regk_iop_sap_out_always = 0x00000001, - regk_iop_sap_out_and = 0x00000002, - regk_iop_sap_out_clk0 = 0x00000000, - regk_iop_sap_out_clk1 = 0x00000001, - regk_iop_sap_out_clk12 = 0x00000004, - regk_iop_sap_out_clk200 = 0x00000000, - regk_iop_sap_out_ext = 0x00000002, - regk_iop_sap_out_gated = 0x00000003, - regk_iop_sap_out_gio0 = 0x00000000, - regk_iop_sap_out_gio1 = 0x00000000, - regk_iop_sap_out_gio16 = 0x00000002, - regk_iop_sap_out_gio17 = 0x00000002, - regk_iop_sap_out_gio24 = 0x00000003, - regk_iop_sap_out_gio25 = 0x00000003, - regk_iop_sap_out_gio8 = 0x00000001, - regk_iop_sap_out_gio9 = 0x00000001, - regk_iop_sap_out_gio_out10 = 0x00000005, - regk_iop_sap_out_gio_out18 = 0x00000006, - regk_iop_sap_out_gio_out2 = 0x00000004, - regk_iop_sap_out_gio_out26 = 0x00000007, - regk_iop_sap_out_inv = 0x00000001, - regk_iop_sap_out_nand = 0x00000003, - regk_iop_sap_out_no = 0x00000000, - regk_iop_sap_out_none = 0x00000000, - regk_iop_sap_out_one = 0x00000001, - regk_iop_sap_out_rw_bus_default = 0x00000000, - regk_iop_sap_out_rw_bus_hi_oe_default = 0x00000000, - regk_iop_sap_out_rw_bus_lo_oe_default = 0x00000000, - regk_iop_sap_out_rw_gen_gated_default = 0x00000000, - regk_iop_sap_out_rw_gio_default = 0x00000000, - regk_iop_sap_out_rw_gio_size = 0x00000020, - regk_iop_sap_out_spu_gio6 = 0x00000002, - regk_iop_sap_out_spu_gio7 = 0x00000003, - regk_iop_sap_out_timer_grp0_tmr2 = 0x00000000, - regk_iop_sap_out_timer_grp0_tmr3 = 0x00000001, - regk_iop_sap_out_timer_grp1_tmr2 = 0x00000002, - regk_iop_sap_out_timer_grp1_tmr3 = 0x00000003, - regk_iop_sap_out_tmr200 = 0x00000001, - regk_iop_sap_out_yes = 0x00000001 -}; -#endif /* __iop_sap_out_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h deleted file mode 100644 index 07050b053bb4..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cfg_defs.h +++ /dev/null @@ -1,726 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cfg_defs_h -#define __iop_sw_cfg_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cfg.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cfg_defs.h iop_sw_cfg.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cfg */ - -/* Register rw_crc_par_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_crc_par_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_crc_par_owner 0 -#define REG_WR_ADDR_iop_sw_cfg_rw_crc_par_owner 0 - -/* Register rw_dmc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_in_owner 4 - -/* Register rw_dmc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_dmc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 -#define REG_WR_ADDR_iop_sw_cfg_rw_dmc_out_owner 8 - -/* Register rw_fifo_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_owner 12 - -/* Register rw_fifo_in_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_in_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_in_extra_owner 16 - -/* Register rw_fifo_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_owner 20 - -/* Register rw_fifo_out_extra_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_fifo_out_extra_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 -#define REG_WR_ADDR_iop_sw_cfg_rw_fifo_out_extra_owner 24 - -/* Register rw_sap_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_in_owner 28 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_in_owner 28 - -/* Register rw_sap_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_sap_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_sap_out_owner 32 -#define REG_WR_ADDR_iop_sw_cfg_rw_sap_out_owner 32 - -/* Register rw_scrc_in_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_in_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_in_owner 36 - -/* Register rw_scrc_out_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_scrc_out_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 -#define REG_WR_ADDR_iop_sw_cfg_rw_scrc_out_owner 40 - -/* Register rw_spu_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 1; - unsigned int dummy1 : 31; -} reg_iop_sw_cfg_rw_spu_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_owner 44 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_owner 44 - -/* Register rw_timer_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_owner 48 - -/* Register rw_timer_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_timer_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_owner 52 - -/* Register rw_trigger_grp0_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp0_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp0_owner 56 - -/* Register rw_trigger_grp1_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp1_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp1_owner 60 - -/* Register rw_trigger_grp2_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp2_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp2_owner 64 - -/* Register rw_trigger_grp3_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp3_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp3_owner 68 - -/* Register rw_trigger_grp4_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp4_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp4_owner 72 - -/* Register rw_trigger_grp5_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp5_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp5_owner 76 - -/* Register rw_trigger_grp6_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp6_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp6_owner 80 - -/* Register rw_trigger_grp7_owner, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_trigger_grp7_owner; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grp7_owner 84 - -/* Register rw_bus_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cfg_rw_bus_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_mask 88 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_mask 88 - -/* Register rw_bus_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cfg_rw_bus_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_oe_mask 92 - -/* Register rw_gio_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_mask 96 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_mask 96 - -/* Register rw_gio_oe_mask, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cfg_rw_gio_oe_mask; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_oe_mask 100 - -/* Register rw_pinmapping, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_byte0 : 2; - unsigned int bus_byte1 : 2; - unsigned int bus_byte2 : 2; - unsigned int bus_byte3 : 2; - unsigned int gio3_0 : 2; - unsigned int gio7_4 : 2; - unsigned int gio11_8 : 2; - unsigned int gio15_12 : 2; - unsigned int gio19_16 : 2; - unsigned int gio23_20 : 2; - unsigned int gio27_24 : 2; - unsigned int gio31_28 : 2; - unsigned int dummy1 : 8; -} reg_iop_sw_cfg_rw_pinmapping; -#define REG_RD_ADDR_iop_sw_cfg_rw_pinmapping 104 -#define REG_WR_ADDR_iop_sw_cfg_rw_pinmapping 104 - -/* Register rw_bus_out_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus_lo : 2; - unsigned int bus_hi : 2; - unsigned int bus_lo_oe : 2; - unsigned int bus_hi_oe : 2; - unsigned int dummy1 : 24; -} reg_iop_sw_cfg_rw_bus_out_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 -#define REG_WR_ADDR_iop_sw_cfg_rw_bus_out_cfg 108 - -/* Register rw_gio_out_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio0 : 3; - unsigned int gio0_oe : 1; - unsigned int gio1 : 3; - unsigned int gio1_oe : 1; - unsigned int gio2 : 3; - unsigned int gio2_oe : 1; - unsigned int gio3 : 3; - unsigned int gio3_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp0_cfg 112 - -/* Register rw_gio_out_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio4 : 3; - unsigned int gio4_oe : 1; - unsigned int gio5 : 3; - unsigned int gio5_oe : 1; - unsigned int gio6 : 3; - unsigned int gio6_oe : 1; - unsigned int gio7 : 3; - unsigned int gio7_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp1_cfg 116 - -/* Register rw_gio_out_grp2_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio8 : 3; - unsigned int gio8_oe : 1; - unsigned int gio9 : 3; - unsigned int gio9_oe : 1; - unsigned int gio10 : 3; - unsigned int gio10_oe : 1; - unsigned int gio11 : 3; - unsigned int gio11_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp2_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp2_cfg 120 - -/* Register rw_gio_out_grp3_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio12 : 3; - unsigned int gio12_oe : 1; - unsigned int gio13 : 3; - unsigned int gio13_oe : 1; - unsigned int gio14 : 3; - unsigned int gio14_oe : 1; - unsigned int gio15 : 3; - unsigned int gio15_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp3_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp3_cfg 124 - -/* Register rw_gio_out_grp4_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio16 : 3; - unsigned int gio16_oe : 1; - unsigned int gio17 : 3; - unsigned int gio17_oe : 1; - unsigned int gio18 : 3; - unsigned int gio18_oe : 1; - unsigned int gio19 : 3; - unsigned int gio19_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp4_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp4_cfg 128 - -/* Register rw_gio_out_grp5_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio20 : 3; - unsigned int gio20_oe : 1; - unsigned int gio21 : 3; - unsigned int gio21_oe : 1; - unsigned int gio22 : 3; - unsigned int gio22_oe : 1; - unsigned int gio23 : 3; - unsigned int gio23_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp5_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp5_cfg 132 - -/* Register rw_gio_out_grp6_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio24 : 3; - unsigned int gio24_oe : 1; - unsigned int gio25 : 3; - unsigned int gio25_oe : 1; - unsigned int gio26 : 3; - unsigned int gio26_oe : 1; - unsigned int gio27 : 3; - unsigned int gio27_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp6_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp6_cfg 136 - -/* Register rw_gio_out_grp7_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int gio28 : 3; - unsigned int gio28_oe : 1; - unsigned int gio29 : 3; - unsigned int gio29_oe : 1; - unsigned int gio30 : 3; - unsigned int gio30_oe : 1; - unsigned int gio31 : 3; - unsigned int gio31_oe : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_gio_out_grp7_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 -#define REG_WR_ADDR_iop_sw_cfg_rw_gio_out_grp7_cfg 140 - -/* Register rw_spu_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int bus0_in : 1; - unsigned int bus1_in : 1; - unsigned int dummy1 : 30; -} reg_iop_sw_cfg_rw_spu_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_spu_cfg 144 -#define REG_WR_ADDR_iop_sw_cfg_rw_spu_cfg 144 - -/* Register rw_timer_grp0_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp0_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp0_cfg 148 - -/* Register rw_timer_grp1_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int ext_clk : 3; - unsigned int tmr0_en : 2; - unsigned int tmr1_en : 2; - unsigned int tmr2_en : 2; - unsigned int tmr3_en : 2; - unsigned int tmr0_dis : 2; - unsigned int tmr1_dis : 2; - unsigned int tmr2_dis : 2; - unsigned int tmr3_dis : 2; - unsigned int dummy1 : 13; -} reg_iop_sw_cfg_rw_timer_grp1_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 -#define REG_WR_ADDR_iop_sw_cfg_rw_timer_grp1_cfg 152 - -/* Register rw_trigger_grps_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int grp0_dis : 1; - unsigned int grp0_en : 1; - unsigned int grp1_dis : 1; - unsigned int grp1_en : 1; - unsigned int grp2_dis : 1; - unsigned int grp2_en : 1; - unsigned int grp3_dis : 1; - unsigned int grp3_en : 1; - unsigned int grp4_dis : 1; - unsigned int grp4_en : 1; - unsigned int grp5_dis : 1; - unsigned int grp5_en : 1; - unsigned int grp6_dis : 1; - unsigned int grp6_en : 1; - unsigned int grp7_dis : 1; - unsigned int grp7_en : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cfg_rw_trigger_grps_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 -#define REG_WR_ADDR_iop_sw_cfg_rw_trigger_grps_cfg 156 - -/* Register rw_pdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int out_strb : 4; - unsigned int in_src : 2; - unsigned int in_size : 3; - unsigned int in_last : 2; - unsigned int in_strb : 4; - unsigned int dummy1 : 17; -} reg_iop_sw_cfg_rw_pdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_pdp_cfg 160 -#define REG_WR_ADDR_iop_sw_cfg_rw_pdp_cfg 160 - -/* Register rw_sdp_cfg, scope iop_sw_cfg, type rw */ -typedef struct { - unsigned int sdp_out_strb : 3; - unsigned int sdp_in_data : 3; - unsigned int sdp_in_last : 2; - unsigned int sdp_in_strb : 3; - unsigned int dummy1 : 21; -} reg_iop_sw_cfg_rw_sdp_cfg; -#define REG_RD_ADDR_iop_sw_cfg_rw_sdp_cfg 164 -#define REG_WR_ADDR_iop_sw_cfg_rw_sdp_cfg 164 - - -/* Constants */ -enum { - regk_iop_sw_cfg_a = 0x00000001, - regk_iop_sw_cfg_b = 0x00000002, - regk_iop_sw_cfg_bus = 0x00000000, - regk_iop_sw_cfg_bus_rot16 = 0x00000002, - regk_iop_sw_cfg_bus_rot24 = 0x00000003, - regk_iop_sw_cfg_bus_rot8 = 0x00000001, - regk_iop_sw_cfg_clk12 = 0x00000000, - regk_iop_sw_cfg_cpu = 0x00000000, - regk_iop_sw_cfg_gated_clk0 = 0x0000000e, - regk_iop_sw_cfg_gated_clk1 = 0x0000000f, - regk_iop_sw_cfg_gio0 = 0x00000004, - regk_iop_sw_cfg_gio1 = 0x00000001, - regk_iop_sw_cfg_gio2 = 0x00000005, - regk_iop_sw_cfg_gio3 = 0x00000002, - regk_iop_sw_cfg_gio4 = 0x00000006, - regk_iop_sw_cfg_gio5 = 0x00000003, - regk_iop_sw_cfg_gio6 = 0x00000007, - regk_iop_sw_cfg_gio7 = 0x00000004, - regk_iop_sw_cfg_gio_in18 = 0x00000002, - regk_iop_sw_cfg_gio_in19 = 0x00000003, - regk_iop_sw_cfg_gio_in20 = 0x00000004, - regk_iop_sw_cfg_gio_in21 = 0x00000005, - regk_iop_sw_cfg_gio_in26 = 0x00000006, - regk_iop_sw_cfg_gio_in27 = 0x00000007, - regk_iop_sw_cfg_gio_in4 = 0x00000000, - regk_iop_sw_cfg_gio_in5 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp0_tmr2 = 0x00000001, - regk_iop_sw_cfg_last_timer_grp1_tmr2 = 0x00000002, - regk_iop_sw_cfg_last_timer_grp1_tmr3 = 0x00000003, - regk_iop_sw_cfg_mpu = 0x00000001, - regk_iop_sw_cfg_none = 0x00000000, - regk_iop_sw_cfg_pdp_out = 0x00000001, - regk_iop_sw_cfg_pdp_out_hi = 0x00000001, - regk_iop_sw_cfg_pdp_out_lo = 0x00000000, - regk_iop_sw_cfg_rw_bus_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_bus_out_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_crc_par_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_dmc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_extra_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_fifo_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_oe_mask_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp2_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp3_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp4_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp5_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp6_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_gio_out_grp7_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_pinmapping_default = 0x00555555, - regk_iop_sw_cfg_rw_sap_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sap_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_in_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_scrc_out_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_sdp_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_spu_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_cfg_default = 0x00000000, - regk_iop_sw_cfg_rw_timer_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp0_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp1_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp2_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp3_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp4_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp5_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp6_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grp7_owner_default = 0x00000000, - regk_iop_sw_cfg_rw_trigger_grps_cfg_default = 0x00000000, - regk_iop_sw_cfg_sdp_out = 0x00000004, - regk_iop_sw_cfg_size16 = 0x00000002, - regk_iop_sw_cfg_size24 = 0x00000003, - regk_iop_sw_cfg_size32 = 0x00000004, - regk_iop_sw_cfg_size8 = 0x00000001, - regk_iop_sw_cfg_spu = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_hi = 0x00000002, - regk_iop_sw_cfg_spu_bus_out0_lo = 0x00000002, - regk_iop_sw_cfg_spu_bus_out1_hi = 0x00000003, - regk_iop_sw_cfg_spu_bus_out1_lo = 0x00000003, - regk_iop_sw_cfg_spu_g0 = 0x00000007, - regk_iop_sw_cfg_spu_g1 = 0x00000007, - regk_iop_sw_cfg_spu_g2 = 0x00000007, - regk_iop_sw_cfg_spu_g3 = 0x00000007, - regk_iop_sw_cfg_spu_g4 = 0x00000007, - regk_iop_sw_cfg_spu_g5 = 0x00000007, - regk_iop_sw_cfg_spu_g6 = 0x00000007, - regk_iop_sw_cfg_spu_g7 = 0x00000007, - regk_iop_sw_cfg_spu_gio0 = 0x00000000, - regk_iop_sw_cfg_spu_gio1 = 0x00000001, - regk_iop_sw_cfg_spu_gio5 = 0x00000005, - regk_iop_sw_cfg_spu_gio6 = 0x00000006, - regk_iop_sw_cfg_spu_gio7 = 0x00000007, - regk_iop_sw_cfg_spu_gio_out0 = 0x00000008, - regk_iop_sw_cfg_spu_gio_out1 = 0x00000009, - regk_iop_sw_cfg_spu_gio_out2 = 0x0000000a, - regk_iop_sw_cfg_spu_gio_out3 = 0x0000000b, - regk_iop_sw_cfg_spu_gio_out4 = 0x0000000c, - regk_iop_sw_cfg_spu_gio_out5 = 0x0000000d, - regk_iop_sw_cfg_spu_gio_out6 = 0x0000000e, - regk_iop_sw_cfg_spu_gio_out7 = 0x0000000f, - regk_iop_sw_cfg_spu_gioout0 = 0x00000000, - regk_iop_sw_cfg_spu_gioout1 = 0x00000000, - regk_iop_sw_cfg_spu_gioout10 = 0x00000007, - regk_iop_sw_cfg_spu_gioout11 = 0x00000007, - regk_iop_sw_cfg_spu_gioout12 = 0x00000007, - regk_iop_sw_cfg_spu_gioout13 = 0x00000007, - regk_iop_sw_cfg_spu_gioout14 = 0x00000007, - regk_iop_sw_cfg_spu_gioout15 = 0x00000007, - regk_iop_sw_cfg_spu_gioout16 = 0x00000007, - regk_iop_sw_cfg_spu_gioout17 = 0x00000007, - regk_iop_sw_cfg_spu_gioout18 = 0x00000007, - regk_iop_sw_cfg_spu_gioout19 = 0x00000007, - regk_iop_sw_cfg_spu_gioout2 = 0x00000001, - regk_iop_sw_cfg_spu_gioout20 = 0x00000007, - regk_iop_sw_cfg_spu_gioout21 = 0x00000007, - regk_iop_sw_cfg_spu_gioout22 = 0x00000007, - regk_iop_sw_cfg_spu_gioout23 = 0x00000007, - regk_iop_sw_cfg_spu_gioout24 = 0x00000007, - regk_iop_sw_cfg_spu_gioout25 = 0x00000007, - regk_iop_sw_cfg_spu_gioout26 = 0x00000007, - regk_iop_sw_cfg_spu_gioout27 = 0x00000007, - regk_iop_sw_cfg_spu_gioout28 = 0x00000007, - regk_iop_sw_cfg_spu_gioout29 = 0x00000007, - regk_iop_sw_cfg_spu_gioout3 = 0x00000001, - regk_iop_sw_cfg_spu_gioout30 = 0x00000007, - regk_iop_sw_cfg_spu_gioout31 = 0x00000007, - regk_iop_sw_cfg_spu_gioout4 = 0x00000002, - regk_iop_sw_cfg_spu_gioout5 = 0x00000002, - regk_iop_sw_cfg_spu_gioout6 = 0x00000003, - regk_iop_sw_cfg_spu_gioout7 = 0x00000003, - regk_iop_sw_cfg_spu_gioout8 = 0x00000007, - regk_iop_sw_cfg_spu_gioout9 = 0x00000007, - regk_iop_sw_cfg_strb_timer_grp0_tmr0 = 0x00000001, - regk_iop_sw_cfg_strb_timer_grp0_tmr1 = 0x00000002, - regk_iop_sw_cfg_strb_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_strb_timer_grp1_tmr1 = 0x00000002, - regk_iop_sw_cfg_timer_grp0 = 0x00000000, - regk_iop_sw_cfg_timer_grp0_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp0_strb0 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb1 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb2 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_strb3 = 0x00000005, - regk_iop_sw_cfg_timer_grp0_tmr0 = 0x00000002, - regk_iop_sw_cfg_timer_grp1 = 0x00000000, - regk_iop_sw_cfg_timer_grp1_rot = 0x00000001, - regk_iop_sw_cfg_timer_grp1_strb0 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb1 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb2 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_strb3 = 0x00000006, - regk_iop_sw_cfg_timer_grp1_tmr0 = 0x00000003, - regk_iop_sw_cfg_trig0_0 = 0x00000000, - regk_iop_sw_cfg_trig0_1 = 0x00000000, - regk_iop_sw_cfg_trig0_2 = 0x00000000, - regk_iop_sw_cfg_trig0_3 = 0x00000000, - regk_iop_sw_cfg_trig1_0 = 0x00000000, - regk_iop_sw_cfg_trig1_1 = 0x00000000, - regk_iop_sw_cfg_trig1_2 = 0x00000000, - regk_iop_sw_cfg_trig1_3 = 0x00000000, - regk_iop_sw_cfg_trig2_0 = 0x00000001, - regk_iop_sw_cfg_trig2_1 = 0x00000001, - regk_iop_sw_cfg_trig2_2 = 0x00000001, - regk_iop_sw_cfg_trig2_3 = 0x00000001, - regk_iop_sw_cfg_trig3_0 = 0x00000001, - regk_iop_sw_cfg_trig3_1 = 0x00000001, - regk_iop_sw_cfg_trig3_2 = 0x00000001, - regk_iop_sw_cfg_trig3_3 = 0x00000001, - regk_iop_sw_cfg_trig4_0 = 0x00000002, - regk_iop_sw_cfg_trig4_1 = 0x00000002, - regk_iop_sw_cfg_trig4_2 = 0x00000002, - regk_iop_sw_cfg_trig4_3 = 0x00000002, - regk_iop_sw_cfg_trig5_0 = 0x00000002, - regk_iop_sw_cfg_trig5_1 = 0x00000002, - regk_iop_sw_cfg_trig5_2 = 0x00000002, - regk_iop_sw_cfg_trig5_3 = 0x00000002, - regk_iop_sw_cfg_trig6_0 = 0x00000003, - regk_iop_sw_cfg_trig6_1 = 0x00000003, - regk_iop_sw_cfg_trig6_2 = 0x00000003, - regk_iop_sw_cfg_trig6_3 = 0x00000003, - regk_iop_sw_cfg_trig7_0 = 0x00000003, - regk_iop_sw_cfg_trig7_1 = 0x00000003, - regk_iop_sw_cfg_trig7_2 = 0x00000003, - regk_iop_sw_cfg_trig7_3 = 0x00000003 -}; -#endif /* __iop_sw_cfg_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h deleted file mode 100644 index b4acdae4f653..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_cpu_defs.h +++ /dev/null @@ -1,523 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_cpu_defs_h -#define __iop_sw_cpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_cpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_cpu_defs.h iop_sw_cpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_cpu */ - -/* Register r_mpu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_mpu_trace 0 - -/* Register r_spu_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_cpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_cpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_cpu, type rw */ -typedef unsigned int reg_iop_sw_cpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_cpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_cpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_cpu, type rs */ -typedef unsigned int reg_iop_sw_cpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_cpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_cpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_cpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_cpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_cpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_cpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_cpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_cpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_cpu, type r */ -typedef unsigned int reg_iop_sw_cpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_cpu_r_gio_in 72 - -/* Register rw_intr0_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_intr0_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr0_mask 76 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr0_mask 76 - -/* Register rw_ack_intr0, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_rw_ack_intr0; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr0 80 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr0 80 - -/* Register r_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_intr0 84 - -/* Register r_masked_intr0, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_0 : 1; - unsigned int mpu_1 : 1; - unsigned int mpu_2 : 1; - unsigned int mpu_3 : 1; - unsigned int mpu_4 : 1; - unsigned int mpu_5 : 1; - unsigned int mpu_6 : 1; - unsigned int mpu_7 : 1; - unsigned int mpu_8 : 1; - unsigned int mpu_9 : 1; - unsigned int mpu_10 : 1; - unsigned int mpu_11 : 1; - unsigned int mpu_12 : 1; - unsigned int mpu_13 : 1; - unsigned int mpu_14 : 1; - unsigned int mpu_15 : 1; - unsigned int spu_0 : 1; - unsigned int spu_1 : 1; - unsigned int spu_2 : 1; - unsigned int spu_3 : 1; - unsigned int spu_4 : 1; - unsigned int spu_5 : 1; - unsigned int spu_6 : 1; - unsigned int spu_7 : 1; - unsigned int spu_8 : 1; - unsigned int spu_9 : 1; - unsigned int spu_10 : 1; - unsigned int spu_11 : 1; - unsigned int spu_12 : 1; - unsigned int spu_13 : 1; - unsigned int spu_14 : 1; - unsigned int spu_15 : 1; -} reg_iop_sw_cpu_r_masked_intr0; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr0 88 - -/* Register rw_intr1_mask, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_rw_intr1_mask; -#define REG_RD_ADDR_iop_sw_cpu_rw_intr1_mask 92 -#define REG_WR_ADDR_iop_sw_cpu_rw_intr1_mask 92 - -/* Register rw_ack_intr1, scope iop_sw_cpu, type rw */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_cpu_rw_ack_intr1; -#define REG_RD_ADDR_iop_sw_cpu_rw_ack_intr1 96 -#define REG_WR_ADDR_iop_sw_cpu_rw_ack_intr1 96 - -/* Register r_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_intr1 100 - -/* Register r_masked_intr1, scope iop_sw_cpu, type r */ -typedef struct { - unsigned int mpu_16 : 1; - unsigned int mpu_17 : 1; - unsigned int mpu_18 : 1; - unsigned int mpu_19 : 1; - unsigned int mpu_20 : 1; - unsigned int mpu_21 : 1; - unsigned int mpu_22 : 1; - unsigned int mpu_23 : 1; - unsigned int mpu_24 : 1; - unsigned int mpu_25 : 1; - unsigned int mpu_26 : 1; - unsigned int mpu_27 : 1; - unsigned int mpu_28 : 1; - unsigned int mpu_29 : 1; - unsigned int mpu_30 : 1; - unsigned int mpu_31 : 1; - unsigned int dmc_in : 1; - unsigned int dmc_out : 1; - unsigned int fifo_in : 1; - unsigned int fifo_out : 1; - unsigned int fifo_in_extra : 1; - unsigned int fifo_out_extra : 1; - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; -} reg_iop_sw_cpu_r_masked_intr1; -#define REG_RD_ADDR_iop_sw_cpu_r_masked_intr1 104 - - -/* Constants */ -enum { - regk_iop_sw_cpu_copy = 0x00000000, - regk_iop_sw_cpu_no = 0x00000000, - regk_iop_sw_cpu_rd = 0x00000002, - regk_iop_sw_cpu_reg_copy = 0x00000001, - regk_iop_sw_cpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr0_mask_default = 0x00000000, - regk_iop_sw_cpu_rw_intr1_mask_default = 0x00000000, - regk_iop_sw_cpu_wr = 0x00000003, - regk_iop_sw_cpu_yes = 0x00000001 -}; -#endif /* __iop_sw_cpu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h deleted file mode 100644 index bc1abb5fb308..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_mpu_defs.h +++ /dev/null @@ -1,649 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_mpu_defs_h -#define __iop_sw_mpu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_mpu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_mpu_defs.h iop_sw_mpu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_mpu */ - -/* Register rw_sw_cfg_owner, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int cfg : 2; - unsigned int dummy1 : 30; -} reg_iop_sw_mpu_rw_sw_cfg_owner; -#define REG_RD_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 -#define REG_WR_ADDR_iop_sw_mpu_rw_sw_cfg_owner 0 - -/* Register r_spu_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_trace 4 - -/* Register r_spu_fsm_trace, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_spu_fsm_trace; -#define REG_RD_ADDR_iop_sw_mpu_r_spu_fsm_trace 8 - -/* Register rw_mc_ctrl, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_mpu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_ctrl 12 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_ctrl 12 - -/* Register rw_mc_data, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_data 16 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_data 16 - -/* Register rw_mc_addr, scope iop_sw_mpu, type rw */ -typedef unsigned int reg_iop_sw_mpu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_mpu_rw_mc_addr 20 -#define REG_WR_ADDR_iop_sw_mpu_rw_mc_addr 20 - -/* Register rs_mc_data, scope iop_sw_mpu, type rs */ -typedef unsigned int reg_iop_sw_mpu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_rs_mc_data 24 - -/* Register r_mc_data, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_mc_data; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_data 28 - -/* Register r_mc_stat, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_mpu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_mpu_r_mc_stat 32 - -/* Register rw_bus_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_clr_mask 36 - -/* Register rw_bus_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_mpu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_set_mask 40 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_set_mask 40 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_clr_mask 44 - -/* Register rw_bus_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_mpu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 -#define REG_WR_ADDR_iop_sw_mpu_rw_bus_oe_set_mask 48 - -/* Register r_bus_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_bus_in; -#define REG_RD_ADDR_iop_sw_mpu_r_bus_in 52 - -/* Register rw_gio_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_clr_mask 56 - -/* Register rw_gio_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_set_mask 60 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_set_mask 60 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_clr_mask 64 - -/* Register rw_gio_oe_set_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_mpu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 -#define REG_WR_ADDR_iop_sw_mpu_rw_gio_oe_set_mask 68 - -/* Register r_gio_in, scope iop_sw_mpu, type r */ -typedef unsigned int reg_iop_sw_mpu_r_gio_in; -#define REG_RD_ADDR_iop_sw_mpu_r_gio_in 72 - -/* Register rw_cpu_intr, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_rw_cpu_intr 76 -#define REG_WR_ADDR_iop_sw_mpu_rw_cpu_intr 76 - -/* Register r_cpu_intr, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int intr16 : 1; - unsigned int intr17 : 1; - unsigned int intr18 : 1; - unsigned int intr19 : 1; - unsigned int intr20 : 1; - unsigned int intr21 : 1; - unsigned int intr22 : 1; - unsigned int intr23 : 1; - unsigned int intr24 : 1; - unsigned int intr25 : 1; - unsigned int intr26 : 1; - unsigned int intr27 : 1; - unsigned int intr28 : 1; - unsigned int intr29 : 1; - unsigned int intr30 : 1; - unsigned int intr31 : 1; -} reg_iop_sw_mpu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_mpu_r_cpu_intr 80 - -/* Register rw_intr_grp0_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp0_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp0_mask 84 - -/* Register rw_ack_intr_grp0, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr1 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr2 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr3 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp0 88 - -/* Register r_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp0 92 - -/* Register r_masked_intr_grp0, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr0 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr1 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr2 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr3 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp0; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp0 96 - -/* Register rw_intr_grp1_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp1_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp1_mask 100 - -/* Register rw_ack_intr_grp1, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr5 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr6 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr7 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp1 104 - -/* Register r_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp1 108 - -/* Register r_masked_intr_grp1, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr4 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr5 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr6 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr7 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp1; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp1 112 - -/* Register rw_intr_grp2_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp2_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp2_mask 116 - -/* Register rw_ack_intr_grp2, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr9 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr10 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr11 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp2 120 - -/* Register r_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp2 124 - -/* Register r_masked_intr_grp2, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr8 : 1; - unsigned int trigger_grp0 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr9 : 1; - unsigned int trigger_grp1 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int spu_intr10 : 1; - unsigned int trigger_grp2 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr11 : 1; - unsigned int trigger_grp3 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp2; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp2 128 - -/* Register rw_intr_grp3_mask, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_rw_intr_grp3_mask; -#define REG_RD_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 -#define REG_WR_ADDR_iop_sw_mpu_rw_intr_grp3_mask 132 - -/* Register rw_ack_intr_grp3, scope iop_sw_mpu, type rw */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int dummy1 : 3; - unsigned int spu_intr13 : 1; - unsigned int dummy2 : 3; - unsigned int spu_intr14 : 1; - unsigned int dummy3 : 3; - unsigned int spu_intr15 : 1; - unsigned int dummy4 : 19; -} reg_iop_sw_mpu_rw_ack_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 -#define REG_WR_ADDR_iop_sw_mpu_rw_ack_intr_grp3 136 - -/* Register r_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_intr_grp3 140 - -/* Register r_masked_intr_grp3, scope iop_sw_mpu, type r */ -typedef struct { - unsigned int spu_intr12 : 1; - unsigned int trigger_grp4 : 1; - unsigned int fifo_out_extra : 1; - unsigned int dmc_out : 1; - unsigned int spu_intr13 : 1; - unsigned int trigger_grp5 : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_in : 1; - unsigned int spu_intr14 : 1; - unsigned int trigger_grp6 : 1; - unsigned int timer_grp0 : 1; - unsigned int fifo_out : 1; - unsigned int spu_intr15 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_mpu_r_masked_intr_grp3; -#define REG_RD_ADDR_iop_sw_mpu_r_masked_intr_grp3 144 - - -/* Constants */ -enum { - regk_iop_sw_mpu_copy = 0x00000000, - regk_iop_sw_mpu_cpu = 0x00000000, - regk_iop_sw_mpu_mpu = 0x00000001, - regk_iop_sw_mpu_no = 0x00000000, - regk_iop_sw_mpu_nop = 0x00000000, - regk_iop_sw_mpu_rd = 0x00000002, - regk_iop_sw_mpu_reg_copy = 0x00000001, - regk_iop_sw_mpu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp0_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp1_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp2_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_intr_grp3_mask_default = 0x00000000, - regk_iop_sw_mpu_rw_sw_cfg_owner_default = 0x00000000, - regk_iop_sw_mpu_set = 0x00000001, - regk_iop_sw_mpu_spu = 0x00000002, - regk_iop_sw_mpu_wr = 0x00000003, - regk_iop_sw_mpu_yes = 0x00000001 -}; -#endif /* __iop_sw_mpu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h deleted file mode 100644 index 82b64360a4d3..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_sw_spu_defs.h +++ /dev/null @@ -1,442 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_sw_spu_defs_h -#define __iop_sw_spu_defs_h - -/* - * This file is autogenerated from - * file: iop_sw_spu.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_sw_spu_defs.h iop_sw_spu.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_sw_spu */ - -/* Register r_mpu_trace, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mpu_trace; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_trace 0 - -/* Register rw_mc_ctrl, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int keep_owner : 1; - unsigned int cmd : 2; - unsigned int size : 3; - unsigned int wr_spu_mem : 1; - unsigned int dummy1 : 25; -} reg_iop_sw_spu_rw_mc_ctrl; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_ctrl 4 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_ctrl 4 - -/* Register rw_mc_data, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_data 8 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_data 8 - -/* Register rw_mc_addr, scope iop_sw_spu, type rw */ -typedef unsigned int reg_iop_sw_spu_rw_mc_addr; -#define REG_RD_ADDR_iop_sw_spu_rw_mc_addr 12 -#define REG_WR_ADDR_iop_sw_spu_rw_mc_addr 12 - -/* Register rs_mc_data, scope iop_sw_spu, type rs */ -typedef unsigned int reg_iop_sw_spu_rs_mc_data; -#define REG_RD_ADDR_iop_sw_spu_rs_mc_data 16 - -/* Register r_mc_data, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_mc_data; -#define REG_RD_ADDR_iop_sw_spu_r_mc_data 20 - -/* Register r_mc_stat, scope iop_sw_spu, type r */ -typedef struct { - unsigned int busy_cpu : 1; - unsigned int busy_mpu : 1; - unsigned int busy_spu : 1; - unsigned int owned_by_cpu : 1; - unsigned int owned_by_mpu : 1; - unsigned int owned_by_spu : 1; - unsigned int dummy1 : 26; -} reg_iop_sw_spu_r_mc_stat; -#define REG_RD_ADDR_iop_sw_spu_r_mc_stat 24 - -/* Register rw_bus_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask 28 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask 28 - -/* Register rw_bus_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int byte2 : 8; - unsigned int byte3 : 8; -} reg_iop_sw_spu_rw_bus_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask 32 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask 32 - -/* Register rw_bus_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_clr_mask 36 - -/* Register rw_bus_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 1; - unsigned int byte1 : 1; - unsigned int byte2 : 1; - unsigned int byte3 : 1; - unsigned int dummy1 : 28; -} reg_iop_sw_spu_rw_bus_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_oe_set_mask 40 - -/* Register r_bus_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_bus_in; -#define REG_RD_ADDR_iop_sw_spu_r_bus_in 44 - -/* Register rw_gio_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask 48 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask 48 - -/* Register rw_gio_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask 52 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask 52 - -/* Register rw_gio_oe_clr_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_clr_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask 56 - -/* Register rw_gio_oe_set_mask, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 32; -} reg_iop_sw_spu_rw_gio_oe_set_mask; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask 60 - -/* Register r_gio_in, scope iop_sw_spu, type r */ -typedef unsigned int reg_iop_sw_spu_r_gio_in; -#define REG_RD_ADDR_iop_sw_spu_r_gio_in 64 - -/* Register rw_bus_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_lo 68 - -/* Register rw_bus_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_clr_mask_hi 72 - -/* Register rw_bus_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte0 : 8; - unsigned int byte1 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_lo 76 - -/* Register rw_bus_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int byte2 : 8; - unsigned int byte3 : 8; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_bus_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 -#define REG_WR_ADDR_iop_sw_spu_rw_bus_set_mask_hi 80 - -/* Register rw_gio_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_lo 84 - -/* Register rw_gio_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_clr_mask_hi 88 - -/* Register rw_gio_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_lo 92 - -/* Register rw_gio_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_set_mask_hi 96 - -/* Register rw_gio_oe_clr_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_lo 100 - -/* Register rw_gio_oe_clr_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_clr_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_clr_mask_hi 104 - -/* Register rw_gio_oe_set_mask_lo, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_lo; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_lo 108 - -/* Register rw_gio_oe_set_mask_hi, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int val : 16; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_gio_oe_set_mask_hi; -#define REG_RD_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 -#define REG_WR_ADDR_iop_sw_spu_rw_gio_oe_set_mask_hi 112 - -/* Register rw_cpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_cpu_intr 116 -#define REG_WR_ADDR_iop_sw_spu_rw_cpu_intr 116 - -/* Register r_cpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_cpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_cpu_intr 120 - -/* Register r_hw_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int trigger_grp0 : 1; - unsigned int trigger_grp1 : 1; - unsigned int trigger_grp2 : 1; - unsigned int trigger_grp3 : 1; - unsigned int trigger_grp4 : 1; - unsigned int trigger_grp5 : 1; - unsigned int trigger_grp6 : 1; - unsigned int trigger_grp7 : 1; - unsigned int timer_grp0 : 1; - unsigned int timer_grp1 : 1; - unsigned int fifo_out : 1; - unsigned int fifo_out_extra : 1; - unsigned int fifo_in : 1; - unsigned int fifo_in_extra : 1; - unsigned int dmc_out : 1; - unsigned int dmc_in : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_hw_intr; -#define REG_RD_ADDR_iop_sw_spu_r_hw_intr 124 - -/* Register rw_mpu_intr, scope iop_sw_spu, type rw */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_rw_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_rw_mpu_intr 128 -#define REG_WR_ADDR_iop_sw_spu_rw_mpu_intr 128 - -/* Register r_mpu_intr, scope iop_sw_spu, type r */ -typedef struct { - unsigned int intr0 : 1; - unsigned int intr1 : 1; - unsigned int intr2 : 1; - unsigned int intr3 : 1; - unsigned int intr4 : 1; - unsigned int intr5 : 1; - unsigned int intr6 : 1; - unsigned int intr7 : 1; - unsigned int intr8 : 1; - unsigned int intr9 : 1; - unsigned int intr10 : 1; - unsigned int intr11 : 1; - unsigned int intr12 : 1; - unsigned int intr13 : 1; - unsigned int intr14 : 1; - unsigned int intr15 : 1; - unsigned int dummy1 : 16; -} reg_iop_sw_spu_r_mpu_intr; -#define REG_RD_ADDR_iop_sw_spu_r_mpu_intr 132 - - -/* Constants */ -enum { - regk_iop_sw_spu_copy = 0x00000000, - regk_iop_sw_spu_no = 0x00000000, - regk_iop_sw_spu_nop = 0x00000000, - regk_iop_sw_spu_rd = 0x00000002, - regk_iop_sw_spu_reg_copy = 0x00000001, - regk_iop_sw_spu_rw_bus_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_bus_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_clr_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_oe_set_mask_default = 0x00000000, - regk_iop_sw_spu_rw_gio_set_mask_default = 0x00000000, - regk_iop_sw_spu_set = 0x00000001, - regk_iop_sw_spu_wr = 0x00000003, - regk_iop_sw_spu_yes = 0x00000001 -}; -#endif /* __iop_sw_spu_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h b/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h deleted file mode 100644 index d944c6ce5f9b..000000000000 --- a/arch/cris/include/arch-v32/mach-a3/mach/hwregs/iop/iop_version_defs.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __iop_version_defs_h -#define __iop_version_defs_h - -/* - * This file is autogenerated from - * file: iop_version.r - * - * by ../../../tools/rdesc/bin/rdes2c -outfile iop_version_defs.h iop_version.r - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope iop_version */ - -/* Register r_version, scope iop_version, type r */ -typedef struct { - unsigned int nr : 8; - unsigned int dummy1 : 24; -} reg_iop_version_r_version; -#define REG_RD_ADDR_iop_version_r_version 0 - - -/* Constants */ -enum { - regk_iop_version_v2_0 = 0x00000002 -}; -#endif /* __iop_version_defs_h */ |