diff options
| author | Jesper Nilsson <jesper@jni.nu> | 2018-03-11 11:05:23 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2018-03-16 10:56:05 +0100 |
| commit | c690eddc2f3b44b24520f4a77cc3a4c9bde7d571 (patch) | |
| tree | b7ba2caa6ebb2e36a529f9bf7182c9e0a73d53c4 /arch/cris/include/arch-v32/mach-fs/mach | |
| parent | bb9d812643d8a121df7d614a2b9c60193a92deb0 (diff) | |
CRIS: Drop support for the CRIS port
The port was added back in 2000 so it's no longer even a good source
of inspiration for newer ports (if it ever was)
The last SoC (ARTPEC-3) with a CRIS main CPU was launched in 2008.
Coupled with time and working developer board hardware being
in low supply, it's time to drop the port from Linux.
So long and thanks for all the fish!
Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/cris/include/arch-v32/mach-fs/mach')
24 files changed, 0 insertions, 5195 deletions
diff --git a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h b/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h deleted file mode 100644 index f9401a3de83c..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/arbiter.h +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_ARBITER_H -#define _ASM_CRIS_ARCH_ARBITER_H - -#define EXT_REGION 0 -#define INT_REGION 1 - -typedef void (watch_callback)(void); - -enum { - arbiter_all_dmas = 0x3ff, - arbiter_cpu = 0xc00, - arbiter_all_clients = 0x3fff -}; - -enum { - arbiter_all_read = 0x55, - arbiter_all_write = 0xaa, - arbiter_all_accesses = 0xff -}; - -int crisv32_arbiter_allocate_bandwidth(int client, int region, - unsigned long bandwidth); -int crisv32_arbiter_watch(unsigned long start, unsigned long size, - unsigned long clients, unsigned long accesses, - watch_callback * cb); -int crisv32_arbiter_unwatch(int id); - -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/dma.h b/arch/cris/include/arch-v32/mach-fs/mach/dma.h deleted file mode 100644 index 53a59944a48b..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/dma.h +++ /dev/null @@ -1,80 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_CRIS_DMA_H -#define _ASM_ARCH_CRIS_DMA_H - -/* Defines for using and allocating dma channels. */ - -#define MAX_DMA_CHANNELS 10 - -#define NETWORK_ETH0_TX_DMA_NBR 0 /* Ethernet 0 out. */ -#define NETWORK_ETH0 RX_DMA_NBR 1 /* Ethernet 0 in. */ - -#define IO_PROC_DMA0_TX_DMA_NBR 2 /* IO processor DMA0 out. */ -#define IO_PROC_DMA0_RX_DMA_NBR 3 /* IO processor DMA0 in. */ - -#define ATA_TX_DMA_NBR 2 /* ATA interface out. */ -#define ATA_RX_DMA_NBR 3 /* ATA interface in. */ - -#define ASYNC_SER2_TX_DMA_NBR 2 /* Asynchronous serial port 2 out. */ -#define ASYNC_SER2_RX_DMA_NBR 3 /* Asynchronous serial port 2 in. */ - -#define IO_PROC_DMA1_TX_DMA_NBR 4 /* IO processor DMA1 out. */ -#define IO_PROC_DMA1_RX_DMA_NBR 5 /* IO processor DMA1 in. */ - -#define ASYNC_SER1_TX_DMA_NBR 4 /* Asynchronous serial port 1 out. */ -#define ASYNC_SER1_RX_DMA_NBR 5 /* Asynchronous serial port 1 in. */ - -#define SYNC_SER0_TX_DMA_NBR 4 /* Synchronous serial port 0 out. */ -#define SYNC_SER0_RX_DMA_NBR 5 /* Synchronous serial port 0 in. */ - -#define EXTDMA0_TX_DMA_NBR 6 /* External DMA 0 out. */ -#define EXTDMA1_RX_DMA_NBR 7 /* External DMA 1 in. */ - -#define ASYNC_SER0_TX_DMA_NBR 6 /* Asynchronous serial port 0 out. */ -#define ASYNC_SER0_RX_DMA_NBR 7 /* Asynchronous serial port 0 in. */ - -#define SYNC_SER1_TX_DMA_NBR 6 /* Synchronous serial port 1 out. */ -#define SYNC_SER1_RX_DMA_NBR 7 /* Synchronous serial port 1 in. */ - -#define NETWORK_ETH1_TX_DMA_NBR 6 /* Ethernet 1 out. */ -#define NETWORK_ETH1_RX_DMA_NBR 7 /* Ethernet 1 in. */ - -#define EXTDMA2_TX_DMA_NBR 8 /* External DMA 2 out. */ -#define EXTDMA3_RX_DMA_NBR 9 /* External DMA 3 in. */ - -#define STRCOP_TX_DMA_NBR 8 /* Stream co-processor out. */ -#define STRCOP_RX_DMA_NBR 9 /* Stream co-processor in. */ - -#define ASYNC_SER3_TX_DMA_NBR 8 /* Asynchronous serial port 3 out. */ -#define ASYNC_SER3_RX_DMA_NBR 9 /* Asynchronous serial port 3 in. */ - -enum dma_owner { - dma_eth0, - dma_eth1, - dma_iop0, - dma_iop1, - dma_ser0, - dma_ser1, - dma_ser2, - dma_ser3, - dma_sser0, - dma_sser1, - dma_ata, - dma_strp, - dma_ext0, - dma_ext1, - dma_ext2, - dma_ext3 -}; - -int crisv32_request_dma(unsigned int dmanr, const char *device_id, - unsigned options, unsigned bandwidth, - enum dma_owner owner); -void crisv32_free_dma(unsigned int dmanr); - -/* Masks used by crisv32_request_dma options: */ -#define DMA_VERBOSE_ON_ERROR 1 -#define DMA_PANIC_ON_ERROR (2|DMA_VERBOSE_ON_ERROR) -#define DMA_INT_MEM 4 - -#endif /* _ASM_ARCH_CRIS_DMA_H */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h deleted file mode 100644 index 092cad384b86..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/bif_core_defs_asm.h +++ /dev/null @@ -1,320 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_core_defs_asm_h -#define __bif_core_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/bif_core_defs_asm.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp1_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp1_cfg___lw___width 6 -#define reg_bif_core_rw_grp1_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp1_cfg___ew___width 3 -#define reg_bif_core_rw_grp1_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp1_cfg___zw___width 3 -#define reg_bif_core_rw_grp1_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp1_cfg___aw___width 2 -#define reg_bif_core_rw_grp1_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp1_cfg___dw___width 2 -#define reg_bif_core_rw_grp1_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp1_cfg___ewb___width 2 -#define reg_bif_core_rw_grp1_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp1_cfg___bw___width 1 -#define reg_bif_core_rw_grp1_cfg___bw___bit 18 -#define reg_bif_core_rw_grp1_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp1_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp1_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp1_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp1_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp1_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp1_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp1_cfg___mode___width 1 -#define reg_bif_core_rw_grp1_cfg___mode___bit 21 -#define reg_bif_core_rw_grp1_cfg_offset 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp2_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp2_cfg___lw___width 6 -#define reg_bif_core_rw_grp2_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp2_cfg___ew___width 3 -#define reg_bif_core_rw_grp2_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp2_cfg___zw___width 3 -#define reg_bif_core_rw_grp2_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp2_cfg___aw___width 2 -#define reg_bif_core_rw_grp2_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp2_cfg___dw___width 2 -#define reg_bif_core_rw_grp2_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp2_cfg___ewb___width 2 -#define reg_bif_core_rw_grp2_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp2_cfg___bw___width 1 -#define reg_bif_core_rw_grp2_cfg___bw___bit 18 -#define reg_bif_core_rw_grp2_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp2_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp2_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp2_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp2_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp2_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp2_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp2_cfg___mode___width 1 -#define reg_bif_core_rw_grp2_cfg___mode___bit 21 -#define reg_bif_core_rw_grp2_cfg_offset 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp3_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp3_cfg___lw___width 6 -#define reg_bif_core_rw_grp3_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp3_cfg___ew___width 3 -#define reg_bif_core_rw_grp3_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp3_cfg___zw___width 3 -#define reg_bif_core_rw_grp3_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp3_cfg___aw___width 2 -#define reg_bif_core_rw_grp3_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp3_cfg___dw___width 2 -#define reg_bif_core_rw_grp3_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp3_cfg___ewb___width 2 -#define reg_bif_core_rw_grp3_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp3_cfg___bw___width 1 -#define reg_bif_core_rw_grp3_cfg___bw___bit 18 -#define reg_bif_core_rw_grp3_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp3_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp3_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp3_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp3_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp3_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp3_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp3_cfg___mode___width 1 -#define reg_bif_core_rw_grp3_cfg___mode___bit 21 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___lsb 24 -#define reg_bif_core_rw_grp3_cfg___gated_csp0___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___lsb 26 -#define reg_bif_core_rw_grp3_cfg___gated_csp1___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___lsb 28 -#define reg_bif_core_rw_grp3_cfg___gated_csp2___width 2 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___lsb 30 -#define reg_bif_core_rw_grp3_cfg___gated_csp3___width 2 -#define reg_bif_core_rw_grp3_cfg_offset 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -#define reg_bif_core_rw_grp4_cfg___lw___lsb 0 -#define reg_bif_core_rw_grp4_cfg___lw___width 6 -#define reg_bif_core_rw_grp4_cfg___ew___lsb 6 -#define reg_bif_core_rw_grp4_cfg___ew___width 3 -#define reg_bif_core_rw_grp4_cfg___zw___lsb 9 -#define reg_bif_core_rw_grp4_cfg___zw___width 3 -#define reg_bif_core_rw_grp4_cfg___aw___lsb 12 -#define reg_bif_core_rw_grp4_cfg___aw___width 2 -#define reg_bif_core_rw_grp4_cfg___dw___lsb 14 -#define reg_bif_core_rw_grp4_cfg___dw___width 2 -#define reg_bif_core_rw_grp4_cfg___ewb___lsb 16 -#define reg_bif_core_rw_grp4_cfg___ewb___width 2 -#define reg_bif_core_rw_grp4_cfg___bw___lsb 18 -#define reg_bif_core_rw_grp4_cfg___bw___width 1 -#define reg_bif_core_rw_grp4_cfg___bw___bit 18 -#define reg_bif_core_rw_grp4_cfg___wr_extend___lsb 19 -#define reg_bif_core_rw_grp4_cfg___wr_extend___width 1 -#define reg_bif_core_rw_grp4_cfg___wr_extend___bit 19 -#define reg_bif_core_rw_grp4_cfg___erc_en___lsb 20 -#define reg_bif_core_rw_grp4_cfg___erc_en___width 1 -#define reg_bif_core_rw_grp4_cfg___erc_en___bit 20 -#define reg_bif_core_rw_grp4_cfg___mode___lsb 21 -#define reg_bif_core_rw_grp4_cfg___mode___width 1 -#define reg_bif_core_rw_grp4_cfg___mode___bit 21 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___lsb 26 -#define reg_bif_core_rw_grp4_cfg___gated_csp4___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___lsb 28 -#define reg_bif_core_rw_grp4_cfg___gated_csp5___width 2 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___lsb 30 -#define reg_bif_core_rw_grp4_cfg___gated_csp6___width 2 -#define reg_bif_core_rw_grp4_cfg_offset 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp0___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp0___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp0___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp0___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp0___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___lsb 15 -#define reg_bif_core_rw_sdram_cfg_grp0___grp_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp0_offset 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___lsb 0 -#define reg_bif_core_rw_sdram_cfg_grp1___bank_sel___width 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___lsb 5 -#define reg_bif_core_rw_sdram_cfg_grp1___ca___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___type___lsb 8 -#define reg_bif_core_rw_sdram_cfg_grp1___type___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___type___bit 8 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___lsb 9 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___bw___bit 9 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___lsb 10 -#define reg_bif_core_rw_sdram_cfg_grp1___sh___width 3 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___lsb 13 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___wmm___bit 13 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___lsb 14 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___width 1 -#define reg_bif_core_rw_sdram_cfg_grp1___sh16___bit 14 -#define reg_bif_core_rw_sdram_cfg_grp1_offset 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_timing___cl___lsb 0 -#define reg_bif_core_rw_sdram_timing___cl___width 3 -#define reg_bif_core_rw_sdram_timing___rcd___lsb 3 -#define reg_bif_core_rw_sdram_timing___rcd___width 3 -#define reg_bif_core_rw_sdram_timing___rp___lsb 6 -#define reg_bif_core_rw_sdram_timing___rp___width 3 -#define reg_bif_core_rw_sdram_timing___rc___lsb 9 -#define reg_bif_core_rw_sdram_timing___rc___width 2 -#define reg_bif_core_rw_sdram_timing___dpl___lsb 11 -#define reg_bif_core_rw_sdram_timing___dpl___width 2 -#define reg_bif_core_rw_sdram_timing___pde___lsb 13 -#define reg_bif_core_rw_sdram_timing___pde___width 1 -#define reg_bif_core_rw_sdram_timing___pde___bit 13 -#define reg_bif_core_rw_sdram_timing___ref___lsb 14 -#define reg_bif_core_rw_sdram_timing___ref___width 2 -#define reg_bif_core_rw_sdram_timing___cpd___lsb 16 -#define reg_bif_core_rw_sdram_timing___cpd___width 1 -#define reg_bif_core_rw_sdram_timing___cpd___bit 16 -#define reg_bif_core_rw_sdram_timing___sdcke___lsb 17 -#define reg_bif_core_rw_sdram_timing___sdcke___width 1 -#define reg_bif_core_rw_sdram_timing___sdcke___bit 17 -#define reg_bif_core_rw_sdram_timing___sdclk___lsb 18 -#define reg_bif_core_rw_sdram_timing___sdclk___width 1 -#define reg_bif_core_rw_sdram_timing___sdclk___bit 18 -#define reg_bif_core_rw_sdram_timing_offset 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -#define reg_bif_core_rw_sdram_cmd___cmd___lsb 0 -#define reg_bif_core_rw_sdram_cmd___cmd___width 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___lsb 3 -#define reg_bif_core_rw_sdram_cmd___mrs_data___width 15 -#define reg_bif_core_rw_sdram_cmd_offset 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -#define reg_bif_core_rs_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_rs_sdram_ref_stat___ok___width 1 -#define reg_bif_core_rs_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_rs_sdram_ref_stat_offset 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -#define reg_bif_core_r_sdram_ref_stat___ok___lsb 0 -#define reg_bif_core_r_sdram_ref_stat___ok___width 1 -#define reg_bif_core_r_sdram_ref_stat___ok___bit 0 -#define reg_bif_core_r_sdram_ref_stat_offset 36 - - -/* Constants */ -#define regk_bif_core_bank2 0x00000000 -#define regk_bif_core_bank4 0x00000001 -#define regk_bif_core_bit10 0x0000000a -#define regk_bif_core_bit11 0x0000000b -#define regk_bif_core_bit12 0x0000000c -#define regk_bif_core_bit13 0x0000000d -#define regk_bif_core_bit14 0x0000000e -#define regk_bif_core_bit15 0x0000000f -#define regk_bif_core_bit16 0x00000010 -#define regk_bif_core_bit17 0x00000011 -#define regk_bif_core_bit18 0x00000012 -#define regk_bif_core_bit19 0x00000013 -#define regk_bif_core_bit20 0x00000014 -#define regk_bif_core_bit21 0x00000015 -#define regk_bif_core_bit22 0x00000016 -#define regk_bif_core_bit23 0x00000017 -#define regk_bif_core_bit24 0x00000018 -#define regk_bif_core_bit25 0x00000019 -#define regk_bif_core_bit26 0x0000001a -#define regk_bif_core_bit27 0x0000001b -#define regk_bif_core_bit28 0x0000001c -#define regk_bif_core_bit29 0x0000001d -#define regk_bif_core_bit9 0x00000009 -#define regk_bif_core_bw16 0x00000001 -#define regk_bif_core_bw32 0x00000000 -#define regk_bif_core_bwe 0x00000000 -#define regk_bif_core_cwe 0x00000001 -#define regk_bif_core_e15us 0x00000001 -#define regk_bif_core_e7800ns 0x00000002 -#define regk_bif_core_grp0 0x00000000 -#define regk_bif_core_grp1 0x00000001 -#define regk_bif_core_mrs 0x00000003 -#define regk_bif_core_no 0x00000000 -#define regk_bif_core_none 0x00000000 -#define regk_bif_core_nop 0x00000000 -#define regk_bif_core_off 0x00000000 -#define regk_bif_core_pre 0x00000002 -#define regk_bif_core_r_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rd 0x00000002 -#define regk_bif_core_ref 0x00000001 -#define regk_bif_core_rs_sdram_ref_stat_default 0x00000001 -#define regk_bif_core_rw_grp1_cfg_default 0x000006cf -#define regk_bif_core_rw_grp2_cfg_default 0x000006cf -#define regk_bif_core_rw_grp3_cfg_default 0x000006cf -#define regk_bif_core_rw_grp4_cfg_default 0x000006cf -#define regk_bif_core_rw_sdram_cfg_grp1_default 0x00000000 -#define regk_bif_core_slf 0x00000004 -#define regk_bif_core_wr 0x00000001 -#define regk_bif_core_yes 0x00000001 -#endif /* __bif_core_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h deleted file mode 100644 index 5b38835b42f7..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/config_defs_asm.h +++ /dev/null @@ -1,132 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __config_defs_asm_h -#define __config_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/config_defs_asm.h ../../rtl/config_regs.r - * id: $Id: config_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register r_bootsel, scope config, type r */ -#define reg_config_r_bootsel___boot_mode___lsb 0 -#define reg_config_r_bootsel___boot_mode___width 3 -#define reg_config_r_bootsel___full_duplex___lsb 3 -#define reg_config_r_bootsel___full_duplex___width 1 -#define reg_config_r_bootsel___full_duplex___bit 3 -#define reg_config_r_bootsel___user___lsb 4 -#define reg_config_r_bootsel___user___width 1 -#define reg_config_r_bootsel___user___bit 4 -#define reg_config_r_bootsel___pll___lsb 5 -#define reg_config_r_bootsel___pll___width 1 -#define reg_config_r_bootsel___pll___bit 5 -#define reg_config_r_bootsel___flash_bw___lsb 6 -#define reg_config_r_bootsel___flash_bw___width 1 -#define reg_config_r_bootsel___flash_bw___bit 6 -#define reg_config_r_bootsel_offset 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -#define reg_config_rw_clk_ctrl___pll___lsb 0 -#define reg_config_rw_clk_ctrl___pll___width 1 -#define reg_config_rw_clk_ctrl___pll___bit 0 -#define reg_config_rw_clk_ctrl___cpu___lsb 1 -#define reg_config_rw_clk_ctrl___cpu___width 1 -#define reg_config_rw_clk_ctrl___cpu___bit 1 -#define reg_config_rw_clk_ctrl___iop___lsb 2 -#define reg_config_rw_clk_ctrl___iop___width 1 -#define reg_config_rw_clk_ctrl___iop___bit 2 -#define reg_config_rw_clk_ctrl___dma01_eth0___lsb 3 -#define reg_config_rw_clk_ctrl___dma01_eth0___width 1 -#define reg_config_rw_clk_ctrl___dma01_eth0___bit 3 -#define reg_config_rw_clk_ctrl___dma23___lsb 4 -#define reg_config_rw_clk_ctrl___dma23___width 1 -#define reg_config_rw_clk_ctrl___dma23___bit 4 -#define reg_config_rw_clk_ctrl___dma45___lsb 5 -#define reg_config_rw_clk_ctrl___dma45___width 1 -#define reg_config_rw_clk_ctrl___dma45___bit 5 -#define reg_config_rw_clk_ctrl___dma67___lsb 6 -#define reg_config_rw_clk_ctrl___dma67___width 1 -#define reg_config_rw_clk_ctrl___dma67___bit 6 -#define reg_config_rw_clk_ctrl___dma89_strcop___lsb 7 -#define reg_config_rw_clk_ctrl___dma89_strcop___width 1 -#define reg_config_rw_clk_ctrl___dma89_strcop___bit 7 -#define reg_config_rw_clk_ctrl___bif___lsb 8 -#define reg_config_rw_clk_ctrl___bif___width 1 -#define reg_config_rw_clk_ctrl___bif___bit 8 -#define reg_config_rw_clk_ctrl___fix_io___lsb 9 -#define reg_config_rw_clk_ctrl___fix_io___width 1 -#define reg_config_rw_clk_ctrl___fix_io___bit 9 -#define reg_config_rw_clk_ctrl_offset 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -#define reg_config_rw_pad_ctrl___usb_susp___lsb 0 -#define reg_config_rw_pad_ctrl___usb_susp___width 1 -#define reg_config_rw_pad_ctrl___usb_susp___bit 0 -#define reg_config_rw_pad_ctrl___phyrst_n___lsb 1 -#define reg_config_rw_pad_ctrl___phyrst_n___width 1 -#define reg_config_rw_pad_ctrl___phyrst_n___bit 1 -#define reg_config_rw_pad_ctrl_offset 8 - - -/* Constants */ -#define regk_config_bw16 0x00000000 -#define regk_config_bw32 0x00000001 -#define regk_config_master 0x00000005 -#define regk_config_nand 0x00000003 -#define regk_config_net_rx 0x00000001 -#define regk_config_net_tx_rx 0x00000002 -#define regk_config_no 0x00000000 -#define regk_config_none 0x00000007 -#define regk_config_nor 0x00000000 -#define regk_config_rw_clk_ctrl_default 0x00000002 -#define regk_config_rw_pad_ctrl_default 0x00000000 -#define regk_config_ser 0x00000004 -#define regk_config_slave 0x00000006 -#define regk_config_yes 0x00000001 -#endif /* __config_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h deleted file mode 100644 index 3d2056892832..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/gio_defs_asm.h +++ /dev/null @@ -1,277 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __gio_defs_asm_h -#define __gio_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/gio_defs_asm.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa_dout, scope gio, type rw */ -#define reg_gio_rw_pa_dout___data___lsb 0 -#define reg_gio_rw_pa_dout___data___width 8 -#define reg_gio_rw_pa_dout_offset 0 - -/* Register r_pa_din, scope gio, type r */ -#define reg_gio_r_pa_din___data___lsb 0 -#define reg_gio_r_pa_din___data___width 8 -#define reg_gio_r_pa_din_offset 4 - -/* Register rw_pa_oe, scope gio, type rw */ -#define reg_gio_rw_pa_oe___oe___lsb 0 -#define reg_gio_rw_pa_oe___oe___width 8 -#define reg_gio_rw_pa_oe_offset 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -#define reg_gio_rw_intr_cfg___pa0___lsb 0 -#define reg_gio_rw_intr_cfg___pa0___width 3 -#define reg_gio_rw_intr_cfg___pa1___lsb 3 -#define reg_gio_rw_intr_cfg___pa1___width 3 -#define reg_gio_rw_intr_cfg___pa2___lsb 6 -#define reg_gio_rw_intr_cfg___pa2___width 3 -#define reg_gio_rw_intr_cfg___pa3___lsb 9 -#define reg_gio_rw_intr_cfg___pa3___width 3 -#define reg_gio_rw_intr_cfg___pa4___lsb 12 -#define reg_gio_rw_intr_cfg___pa4___width 3 -#define reg_gio_rw_intr_cfg___pa5___lsb 15 -#define reg_gio_rw_intr_cfg___pa5___width 3 -#define reg_gio_rw_intr_cfg___pa6___lsb 18 -#define reg_gio_rw_intr_cfg___pa6___width 3 -#define reg_gio_rw_intr_cfg___pa7___lsb 21 -#define reg_gio_rw_intr_cfg___pa7___width 3 -#define reg_gio_rw_intr_cfg_offset 12 - -/* Register rw_intr_mask, scope gio, type rw */ -#define reg_gio_rw_intr_mask___pa0___lsb 0 -#define reg_gio_rw_intr_mask___pa0___width 1 -#define reg_gio_rw_intr_mask___pa0___bit 0 -#define reg_gio_rw_intr_mask___pa1___lsb 1 -#define reg_gio_rw_intr_mask___pa1___width 1 -#define reg_gio_rw_intr_mask___pa1___bit 1 -#define reg_gio_rw_intr_mask___pa2___lsb 2 -#define reg_gio_rw_intr_mask___pa2___width 1 -#define reg_gio_rw_intr_mask___pa2___bit 2 -#define reg_gio_rw_intr_mask___pa3___lsb 3 -#define reg_gio_rw_intr_mask___pa3___width 1 -#define reg_gio_rw_intr_mask___pa3___bit 3 -#define reg_gio_rw_intr_mask___pa4___lsb 4 -#define reg_gio_rw_intr_mask___pa4___width 1 -#define reg_gio_rw_intr_mask___pa4___bit 4 -#define reg_gio_rw_intr_mask___pa5___lsb 5 -#define reg_gio_rw_intr_mask___pa5___width 1 -#define reg_gio_rw_intr_mask___pa5___bit 5 -#define reg_gio_rw_intr_mask___pa6___lsb 6 -#define reg_gio_rw_intr_mask___pa6___width 1 -#define reg_gio_rw_intr_mask___pa6___bit 6 -#define reg_gio_rw_intr_mask___pa7___lsb 7 -#define reg_gio_rw_intr_mask___pa7___width 1 -#define reg_gio_rw_intr_mask___pa7___bit 7 -#define reg_gio_rw_intr_mask_offset 16 - -/* Register rw_ack_intr, scope gio, type rw */ -#define reg_gio_rw_ack_intr___pa0___lsb 0 -#define reg_gio_rw_ack_intr___pa0___width 1 -#define reg_gio_rw_ack_intr___pa0___bit 0 -#define reg_gio_rw_ack_intr___pa1___lsb 1 -#define reg_gio_rw_ack_intr___pa1___width 1 -#define reg_gio_rw_ack_intr___pa1___bit 1 -#define reg_gio_rw_ack_intr___pa2___lsb 2 -#define reg_gio_rw_ack_intr___pa2___width 1 -#define reg_gio_rw_ack_intr___pa2___bit 2 -#define reg_gio_rw_ack_intr___pa3___lsb 3 -#define reg_gio_rw_ack_intr___pa3___width 1 -#define reg_gio_rw_ack_intr___pa3___bit 3 -#define reg_gio_rw_ack_intr___pa4___lsb 4 -#define reg_gio_rw_ack_intr___pa4___width 1 -#define reg_gio_rw_ack_intr___pa4___bit 4 -#define reg_gio_rw_ack_intr___pa5___lsb 5 -#define reg_gio_rw_ack_intr___pa5___width 1 -#define reg_gio_rw_ack_intr___pa5___bit 5 -#define reg_gio_rw_ack_intr___pa6___lsb 6 -#define reg_gio_rw_ack_intr___pa6___width 1 -#define reg_gio_rw_ack_intr___pa6___bit 6 -#define reg_gio_rw_ack_intr___pa7___lsb 7 -#define reg_gio_rw_ack_intr___pa7___width 1 -#define reg_gio_rw_ack_intr___pa7___bit 7 -#define reg_gio_rw_ack_intr_offset 20 - -/* Register r_intr, scope gio, type r */ -#define reg_gio_r_intr___pa0___lsb 0 -#define reg_gio_r_intr___pa0___width 1 -#define reg_gio_r_intr___pa0___bit 0 -#define reg_gio_r_intr___pa1___lsb 1 -#define reg_gio_r_intr___pa1___width 1 -#define reg_gio_r_intr___pa1___bit 1 -#define reg_gio_r_intr___pa2___lsb 2 -#define reg_gio_r_intr___pa2___width 1 -#define reg_gio_r_intr___pa2___bit 2 -#define reg_gio_r_intr___pa3___lsb 3 -#define reg_gio_r_intr___pa3___width 1 -#define reg_gio_r_intr___pa3___bit 3 -#define reg_gio_r_intr___pa4___lsb 4 -#define reg_gio_r_intr___pa4___width 1 -#define reg_gio_r_intr___pa4___bit 4 -#define reg_gio_r_intr___pa5___lsb 5 -#define reg_gio_r_intr___pa5___width 1 -#define reg_gio_r_intr___pa5___bit 5 -#define reg_gio_r_intr___pa6___lsb 6 -#define reg_gio_r_intr___pa6___width 1 -#define reg_gio_r_intr___pa6___bit 6 -#define reg_gio_r_intr___pa7___lsb 7 -#define reg_gio_r_intr___pa7___width 1 -#define reg_gio_r_intr___pa7___bit 7 -#define reg_gio_r_intr_offset 24 - -/* Register r_masked_intr, scope gio, type r */ -#define reg_gio_r_masked_intr___pa0___lsb 0 -#define reg_gio_r_masked_intr___pa0___width 1 -#define reg_gio_r_masked_intr___pa0___bit 0 -#define reg_gio_r_masked_intr___pa1___lsb 1 -#define reg_gio_r_masked_intr___pa1___width 1 -#define reg_gio_r_masked_intr___pa1___bit 1 -#define reg_gio_r_masked_intr___pa2___lsb 2 -#define reg_gio_r_masked_intr___pa2___width 1 -#define reg_gio_r_masked_intr___pa2___bit 2 -#define reg_gio_r_masked_intr___pa3___lsb 3 -#define reg_gio_r_masked_intr___pa3___width 1 -#define reg_gio_r_masked_intr___pa3___bit 3 -#define reg_gio_r_masked_intr___pa4___lsb 4 -#define reg_gio_r_masked_intr___pa4___width 1 -#define reg_gio_r_masked_intr___pa4___bit 4 -#define reg_gio_r_masked_intr___pa5___lsb 5 -#define reg_gio_r_masked_intr___pa5___width 1 -#define reg_gio_r_masked_intr___pa5___bit 5 -#define reg_gio_r_masked_intr___pa6___lsb 6 -#define reg_gio_r_masked_intr___pa6___width 1 -#define reg_gio_r_masked_intr___pa6___bit 6 -#define reg_gio_r_masked_intr___pa7___lsb 7 -#define reg_gio_r_masked_intr___pa7___width 1 -#define reg_gio_r_masked_intr___pa7___bit 7 -#define reg_gio_r_masked_intr_offset 28 - -/* Register rw_pb_dout, scope gio, type rw */ -#define reg_gio_rw_pb_dout___data___lsb 0 -#define reg_gio_rw_pb_dout___data___width 18 -#define reg_gio_rw_pb_dout_offset 32 - -/* Register r_pb_din, scope gio, type r */ -#define reg_gio_r_pb_din___data___lsb 0 -#define reg_gio_r_pb_din___data___width 18 -#define reg_gio_r_pb_din_offset 36 - -/* Register rw_pb_oe, scope gio, type rw */ -#define reg_gio_rw_pb_oe___oe___lsb 0 -#define reg_gio_rw_pb_oe___oe___width 18 -#define reg_gio_rw_pb_oe_offset 40 - -/* Register rw_pc_dout, scope gio, type rw */ -#define reg_gio_rw_pc_dout___data___lsb 0 -#define reg_gio_rw_pc_dout___data___width 18 -#define reg_gio_rw_pc_dout_offset 48 - -/* Register r_pc_din, scope gio, type r */ -#define reg_gio_r_pc_din___data___lsb 0 -#define reg_gio_r_pc_din___data___width 18 -#define reg_gio_r_pc_din_offset 52 - -/* Register rw_pc_oe, scope gio, type rw */ -#define reg_gio_rw_pc_oe___oe___lsb 0 -#define reg_gio_rw_pc_oe___oe___width 18 -#define reg_gio_rw_pc_oe_offset 56 - -/* Register rw_pd_dout, scope gio, type rw */ -#define reg_gio_rw_pd_dout___data___lsb 0 -#define reg_gio_rw_pd_dout___data___width 18 -#define reg_gio_rw_pd_dout_offset 64 - -/* Register r_pd_din, scope gio, type r */ -#define reg_gio_r_pd_din___data___lsb 0 -#define reg_gio_r_pd_din___data___width 18 -#define reg_gio_r_pd_din_offset 68 - -/* Register rw_pd_oe, scope gio, type rw */ -#define reg_gio_rw_pd_oe___oe___lsb 0 -#define reg_gio_rw_pd_oe___oe___width 18 -#define reg_gio_rw_pd_oe_offset 72 - -/* Register rw_pe_dout, scope gio, type rw */ -#define reg_gio_rw_pe_dout___data___lsb 0 -#define reg_gio_rw_pe_dout___data___width 18 -#define reg_gio_rw_pe_dout_offset 80 - -/* Register r_pe_din, scope gio, type r */ -#define reg_gio_r_pe_din___data___lsb 0 -#define reg_gio_r_pe_din___data___width 18 -#define reg_gio_r_pe_din_offset 84 - -/* Register rw_pe_oe, scope gio, type rw */ -#define reg_gio_rw_pe_oe___oe___lsb 0 -#define reg_gio_rw_pe_oe___oe___width 18 -#define reg_gio_rw_pe_oe_offset 88 - - -/* Constants */ -#define regk_gio_anyedge 0x00000007 -#define regk_gio_hi 0x00000001 -#define regk_gio_lo 0x00000002 -#define regk_gio_negedge 0x00000006 -#define regk_gio_no 0x00000000 -#define regk_gio_off 0x00000000 -#define regk_gio_posedge 0x00000005 -#define regk_gio_rw_intr_cfg_default 0x00000000 -#define regk_gio_rw_intr_mask_default 0x00000000 -#define regk_gio_rw_pa_oe_default 0x00000000 -#define regk_gio_rw_pb_oe_default 0x00000000 -#define regk_gio_rw_pc_oe_default 0x00000000 -#define regk_gio_rw_pd_oe_default 0x00000000 -#define regk_gio_rw_pe_oe_default 0x00000000 -#define regk_gio_set 0x00000003 -#define regk_gio_yes 0x00000001 -#endif /* __gio_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h deleted file mode 100644 index 99968cfa446a..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/pinmux_defs_asm.h +++ /dev/null @@ -1,633 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pinmux_defs_asm_h -#define __pinmux_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/pinmux_defs_asm.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs_asm.h,v 1.1 2007/04/11 11:00:39 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_pa, scope pinmux, type rw */ -#define reg_pinmux_rw_pa___pa0___lsb 0 -#define reg_pinmux_rw_pa___pa0___width 1 -#define reg_pinmux_rw_pa___pa0___bit 0 -#define reg_pinmux_rw_pa___pa1___lsb 1 -#define reg_pinmux_rw_pa___pa1___width 1 -#define reg_pinmux_rw_pa___pa1___bit 1 -#define reg_pinmux_rw_pa___pa2___lsb 2 -#define reg_pinmux_rw_pa___pa2___width 1 -#define reg_pinmux_rw_pa___pa2___bit 2 -#define reg_pinmux_rw_pa___pa3___lsb 3 -#define reg_pinmux_rw_pa___pa3___width 1 -#define reg_pinmux_rw_pa___pa3___bit 3 -#define reg_pinmux_rw_pa___pa4___lsb 4 -#define reg_pinmux_rw_pa___pa4___width 1 -#define reg_pinmux_rw_pa___pa4___bit 4 -#define reg_pinmux_rw_pa___pa5___lsb 5 -#define reg_pinmux_rw_pa___pa5___width 1 -#define reg_pinmux_rw_pa___pa5___bit 5 -#define reg_pinmux_rw_pa___pa6___lsb 6 -#define reg_pinmux_rw_pa___pa6___width 1 -#define reg_pinmux_rw_pa___pa6___bit 6 -#define reg_pinmux_rw_pa___pa7___lsb 7 -#define reg_pinmux_rw_pa___pa7___width 1 -#define reg_pinmux_rw_pa___pa7___bit 7 -#define reg_pinmux_rw_pa___csp2_n___lsb 8 -#define reg_pinmux_rw_pa___csp2_n___width 1 -#define reg_pinmux_rw_pa___csp2_n___bit 8 -#define reg_pinmux_rw_pa___csp3_n___lsb 9 -#define reg_pinmux_rw_pa___csp3_n___width 1 -#define reg_pinmux_rw_pa___csp3_n___bit 9 -#define reg_pinmux_rw_pa___csp5_n___lsb 10 -#define reg_pinmux_rw_pa___csp5_n___width 1 -#define reg_pinmux_rw_pa___csp5_n___bit 10 -#define reg_pinmux_rw_pa___csp6_n___lsb 11 -#define reg_pinmux_rw_pa___csp6_n___width 1 -#define reg_pinmux_rw_pa___csp6_n___bit 11 -#define reg_pinmux_rw_pa___hsh4___lsb 12 -#define reg_pinmux_rw_pa___hsh4___width 1 -#define reg_pinmux_rw_pa___hsh4___bit 12 -#define reg_pinmux_rw_pa___hsh5___lsb 13 -#define reg_pinmux_rw_pa___hsh5___width 1 -#define reg_pinmux_rw_pa___hsh5___bit 13 -#define reg_pinmux_rw_pa___hsh6___lsb 14 -#define reg_pinmux_rw_pa___hsh6___width 1 -#define reg_pinmux_rw_pa___hsh6___bit 14 -#define reg_pinmux_rw_pa___hsh7___lsb 15 -#define reg_pinmux_rw_pa___hsh7___width 1 -#define reg_pinmux_rw_pa___hsh7___bit 15 -#define reg_pinmux_rw_pa_offset 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -#define reg_pinmux_rw_hwprot___ser1___lsb 0 -#define reg_pinmux_rw_hwprot___ser1___width 1 -#define reg_pinmux_rw_hwprot___ser1___bit 0 -#define reg_pinmux_rw_hwprot___ser2___lsb 1 -#define reg_pinmux_rw_hwprot___ser2___width 1 -#define reg_pinmux_rw_hwprot___ser2___bit 1 -#define reg_pinmux_rw_hwprot___ser3___lsb 2 -#define reg_pinmux_rw_hwprot___ser3___width 1 -#define reg_pinmux_rw_hwprot___ser3___bit 2 -#define reg_pinmux_rw_hwprot___sser0___lsb 3 -#define reg_pinmux_rw_hwprot___sser0___width 1 -#define reg_pinmux_rw_hwprot___sser0___bit 3 -#define reg_pinmux_rw_hwprot___sser1___lsb 4 -#define reg_pinmux_rw_hwprot___sser1___width 1 -#define reg_pinmux_rw_hwprot___sser1___bit 4 -#define reg_pinmux_rw_hwprot___ata0___lsb 5 -#define reg_pinmux_rw_hwprot___ata0___width 1 -#define reg_pinmux_rw_hwprot___ata0___bit 5 -#define reg_pinmux_rw_hwprot___ata1___lsb 6 -#define reg_pinmux_rw_hwprot___ata1___width 1 -#define reg_pinmux_rw_hwprot___ata1___bit 6 -#define reg_pinmux_rw_hwprot___ata2___lsb 7 -#define reg_pinmux_rw_hwprot___ata2___width 1 -#define reg_pinmux_rw_hwprot___ata2___bit 7 -#define reg_pinmux_rw_hwprot___ata3___lsb 8 -#define reg_pinmux_rw_hwprot___ata3___width 1 -#define reg_pinmux_rw_hwprot___ata3___bit 8 -#define reg_pinmux_rw_hwprot___ata___lsb 9 -#define reg_pinmux_rw_hwprot___ata___width 1 -#define reg_pinmux_rw_hwprot___ata___bit 9 -#define reg_pinmux_rw_hwprot___eth1___lsb 10 -#define reg_pinmux_rw_hwprot___eth1___width 1 -#define reg_pinmux_rw_hwprot___eth1___bit 10 -#define reg_pinmux_rw_hwprot___eth1_mgm___lsb 11 -#define reg_pinmux_rw_hwprot___eth1_mgm___width 1 -#define reg_pinmux_rw_hwprot___eth1_mgm___bit 11 -#define reg_pinmux_rw_hwprot___timer___lsb 12 -#define reg_pinmux_rw_hwprot___timer___width 1 -#define reg_pinmux_rw_hwprot___timer___bit 12 -#define reg_pinmux_rw_hwprot___p21___lsb 13 -#define reg_pinmux_rw_hwprot___p21___width 1 -#define reg_pinmux_rw_hwprot___p21___bit 13 -#define reg_pinmux_rw_hwprot_offset 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_gio___pb0___lsb 0 -#define reg_pinmux_rw_pb_gio___pb0___width 1 -#define reg_pinmux_rw_pb_gio___pb0___bit 0 -#define reg_pinmux_rw_pb_gio___pb1___lsb 1 -#define reg_pinmux_rw_pb_gio___pb1___width 1 -#define reg_pinmux_rw_pb_gio___pb1___bit 1 -#define reg_pinmux_rw_pb_gio___pb2___lsb 2 -#define reg_pinmux_rw_pb_gio___pb2___width 1 -#define reg_pinmux_rw_pb_gio___pb2___bit 2 -#define reg_pinmux_rw_pb_gio___pb3___lsb 3 -#define reg_pinmux_rw_pb_gio___pb3___width 1 -#define reg_pinmux_rw_pb_gio___pb3___bit 3 -#define reg_pinmux_rw_pb_gio___pb4___lsb 4 -#define reg_pinmux_rw_pb_gio___pb4___width 1 -#define reg_pinmux_rw_pb_gio___pb4___bit 4 -#define reg_pinmux_rw_pb_gio___pb5___lsb 5 -#define reg_pinmux_rw_pb_gio___pb5___width 1 -#define reg_pinmux_rw_pb_gio___pb5___bit 5 -#define reg_pinmux_rw_pb_gio___pb6___lsb 6 -#define reg_pinmux_rw_pb_gio___pb6___width 1 -#define reg_pinmux_rw_pb_gio___pb6___bit 6 -#define reg_pinmux_rw_pb_gio___pb7___lsb 7 -#define reg_pinmux_rw_pb_gio___pb7___width 1 -#define reg_pinmux_rw_pb_gio___pb7___bit 7 -#define reg_pinmux_rw_pb_gio___pb8___lsb 8 -#define reg_pinmux_rw_pb_gio___pb8___width 1 -#define reg_pinmux_rw_pb_gio___pb8___bit 8 -#define reg_pinmux_rw_pb_gio___pb9___lsb 9 -#define reg_pinmux_rw_pb_gio___pb9___width 1 -#define reg_pinmux_rw_pb_gio___pb9___bit 9 -#define reg_pinmux_rw_pb_gio___pb10___lsb 10 -#define reg_pinmux_rw_pb_gio___pb10___width 1 -#define reg_pinmux_rw_pb_gio___pb10___bit 10 -#define reg_pinmux_rw_pb_gio___pb11___lsb 11 -#define reg_pinmux_rw_pb_gio___pb11___width 1 -#define reg_pinmux_rw_pb_gio___pb11___bit 11 -#define reg_pinmux_rw_pb_gio___pb12___lsb 12 -#define reg_pinmux_rw_pb_gio___pb12___width 1 -#define reg_pinmux_rw_pb_gio___pb12___bit 12 -#define reg_pinmux_rw_pb_gio___pb13___lsb 13 -#define reg_pinmux_rw_pb_gio___pb13___width 1 -#define reg_pinmux_rw_pb_gio___pb13___bit 13 -#define reg_pinmux_rw_pb_gio___pb14___lsb 14 -#define reg_pinmux_rw_pb_gio___pb14___width 1 -#define reg_pinmux_rw_pb_gio___pb14___bit 14 -#define reg_pinmux_rw_pb_gio___pb15___lsb 15 -#define reg_pinmux_rw_pb_gio___pb15___width 1 -#define reg_pinmux_rw_pb_gio___pb15___bit 15 -#define reg_pinmux_rw_pb_gio___pb16___lsb 16 -#define reg_pinmux_rw_pb_gio___pb16___width 1 -#define reg_pinmux_rw_pb_gio___pb16___bit 16 -#define reg_pinmux_rw_pb_gio___pb17___lsb 17 -#define reg_pinmux_rw_pb_gio___pb17___width 1 -#define reg_pinmux_rw_pb_gio___pb17___bit 17 -#define reg_pinmux_rw_pb_gio_offset 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pb_iop___pb0___lsb 0 -#define reg_pinmux_rw_pb_iop___pb0___width 1 -#define reg_pinmux_rw_pb_iop___pb0___bit 0 -#define reg_pinmux_rw_pb_iop___pb1___lsb 1 -#define reg_pinmux_rw_pb_iop___pb1___width 1 -#define reg_pinmux_rw_pb_iop___pb1___bit 1 -#define reg_pinmux_rw_pb_iop___pb2___lsb 2 -#define reg_pinmux_rw_pb_iop___pb2___width 1 -#define reg_pinmux_rw_pb_iop___pb2___bit 2 -#define reg_pinmux_rw_pb_iop___pb3___lsb 3 -#define reg_pinmux_rw_pb_iop___pb3___width 1 -#define reg_pinmux_rw_pb_iop___pb3___bit 3 -#define reg_pinmux_rw_pb_iop___pb4___lsb 4 -#define reg_pinmux_rw_pb_iop___pb4___width 1 -#define reg_pinmux_rw_pb_iop___pb4___bit 4 -#define reg_pinmux_rw_pb_iop___pb5___lsb 5 -#define reg_pinmux_rw_pb_iop___pb5___width 1 -#define reg_pinmux_rw_pb_iop___pb5___bit 5 -#define reg_pinmux_rw_pb_iop___pb6___lsb 6 -#define reg_pinmux_rw_pb_iop___pb6___width 1 -#define reg_pinmux_rw_pb_iop___pb6___bit 6 -#define reg_pinmux_rw_pb_iop___pb7___lsb 7 -#define reg_pinmux_rw_pb_iop___pb7___width 1 -#define reg_pinmux_rw_pb_iop___pb7___bit 7 -#define reg_pinmux_rw_pb_iop___pb8___lsb 8 -#define reg_pinmux_rw_pb_iop___pb8___width 1 -#define reg_pinmux_rw_pb_iop___pb8___bit 8 -#define reg_pinmux_rw_pb_iop___pb9___lsb 9 -#define reg_pinmux_rw_pb_iop___pb9___width 1 -#define reg_pinmux_rw_pb_iop___pb9___bit 9 -#define reg_pinmux_rw_pb_iop___pb10___lsb 10 -#define reg_pinmux_rw_pb_iop___pb10___width 1 -#define reg_pinmux_rw_pb_iop___pb10___bit 10 -#define reg_pinmux_rw_pb_iop___pb11___lsb 11 -#define reg_pinmux_rw_pb_iop___pb11___width 1 -#define reg_pinmux_rw_pb_iop___pb11___bit 11 -#define reg_pinmux_rw_pb_iop___pb12___lsb 12 -#define reg_pinmux_rw_pb_iop___pb12___width 1 -#define reg_pinmux_rw_pb_iop___pb12___bit 12 -#define reg_pinmux_rw_pb_iop___pb13___lsb 13 -#define reg_pinmux_rw_pb_iop___pb13___width 1 -#define reg_pinmux_rw_pb_iop___pb13___bit 13 -#define reg_pinmux_rw_pb_iop___pb14___lsb 14 -#define reg_pinmux_rw_pb_iop___pb14___width 1 -#define reg_pinmux_rw_pb_iop___pb14___bit 14 -#define reg_pinmux_rw_pb_iop___pb15___lsb 15 -#define reg_pinmux_rw_pb_iop___pb15___width 1 -#define reg_pinmux_rw_pb_iop___pb15___bit 15 -#define reg_pinmux_rw_pb_iop___pb16___lsb 16 -#define reg_pinmux_rw_pb_iop___pb16___width 1 -#define reg_pinmux_rw_pb_iop___pb16___bit 16 -#define reg_pinmux_rw_pb_iop___pb17___lsb 17 -#define reg_pinmux_rw_pb_iop___pb17___width 1 -#define reg_pinmux_rw_pb_iop___pb17___bit 17 -#define reg_pinmux_rw_pb_iop_offset 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_gio___pc0___lsb 0 -#define reg_pinmux_rw_pc_gio___pc0___width 1 -#define reg_pinmux_rw_pc_gio___pc0___bit 0 -#define reg_pinmux_rw_pc_gio___pc1___lsb 1 -#define reg_pinmux_rw_pc_gio___pc1___width 1 -#define reg_pinmux_rw_pc_gio___pc1___bit 1 -#define reg_pinmux_rw_pc_gio___pc2___lsb 2 -#define reg_pinmux_rw_pc_gio___pc2___width 1 -#define reg_pinmux_rw_pc_gio___pc2___bit 2 -#define reg_pinmux_rw_pc_gio___pc3___lsb 3 -#define reg_pinmux_rw_pc_gio___pc3___width 1 -#define reg_pinmux_rw_pc_gio___pc3___bit 3 -#define reg_pinmux_rw_pc_gio___pc4___lsb 4 -#define reg_pinmux_rw_pc_gio___pc4___width 1 -#define reg_pinmux_rw_pc_gio___pc4___bit 4 -#define reg_pinmux_rw_pc_gio___pc5___lsb 5 -#define reg_pinmux_rw_pc_gio___pc5___width 1 -#define reg_pinmux_rw_pc_gio___pc5___bit 5 -#define reg_pinmux_rw_pc_gio___pc6___lsb 6 -#define reg_pinmux_rw_pc_gio___pc6___width 1 -#define reg_pinmux_rw_pc_gio___pc6___bit 6 -#define reg_pinmux_rw_pc_gio___pc7___lsb 7 -#define reg_pinmux_rw_pc_gio___pc7___width 1 -#define reg_pinmux_rw_pc_gio___pc7___bit 7 -#define reg_pinmux_rw_pc_gio___pc8___lsb 8 -#define reg_pinmux_rw_pc_gio___pc8___width 1 -#define reg_pinmux_rw_pc_gio___pc8___bit 8 -#define reg_pinmux_rw_pc_gio___pc9___lsb 9 -#define reg_pinmux_rw_pc_gio___pc9___width 1 -#define reg_pinmux_rw_pc_gio___pc9___bit 9 -#define reg_pinmux_rw_pc_gio___pc10___lsb 10 -#define reg_pinmux_rw_pc_gio___pc10___width 1 -#define reg_pinmux_rw_pc_gio___pc10___bit 10 -#define reg_pinmux_rw_pc_gio___pc11___lsb 11 -#define reg_pinmux_rw_pc_gio___pc11___width 1 -#define reg_pinmux_rw_pc_gio___pc11___bit 11 -#define reg_pinmux_rw_pc_gio___pc12___lsb 12 -#define reg_pinmux_rw_pc_gio___pc12___width 1 -#define reg_pinmux_rw_pc_gio___pc12___bit 12 -#define reg_pinmux_rw_pc_gio___pc13___lsb 13 -#define reg_pinmux_rw_pc_gio___pc13___width 1 -#define reg_pinmux_rw_pc_gio___pc13___bit 13 -#define reg_pinmux_rw_pc_gio___pc14___lsb 14 -#define reg_pinmux_rw_pc_gio___pc14___width 1 -#define reg_pinmux_rw_pc_gio___pc14___bit 14 -#define reg_pinmux_rw_pc_gio___pc15___lsb 15 -#define reg_pinmux_rw_pc_gio___pc15___width 1 -#define reg_pinmux_rw_pc_gio___pc15___bit 15 -#define reg_pinmux_rw_pc_gio___pc16___lsb 16 -#define reg_pinmux_rw_pc_gio___pc16___width 1 -#define reg_pinmux_rw_pc_gio___pc16___bit 16 -#define reg_pinmux_rw_pc_gio___pc17___lsb 17 -#define reg_pinmux_rw_pc_gio___pc17___width 1 -#define reg_pinmux_rw_pc_gio___pc17___bit 17 -#define reg_pinmux_rw_pc_gio_offset 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pc_iop___pc0___lsb 0 -#define reg_pinmux_rw_pc_iop___pc0___width 1 -#define reg_pinmux_rw_pc_iop___pc0___bit 0 -#define reg_pinmux_rw_pc_iop___pc1___lsb 1 -#define reg_pinmux_rw_pc_iop___pc1___width 1 -#define reg_pinmux_rw_pc_iop___pc1___bit 1 -#define reg_pinmux_rw_pc_iop___pc2___lsb 2 -#define reg_pinmux_rw_pc_iop___pc2___width 1 -#define reg_pinmux_rw_pc_iop___pc2___bit 2 -#define reg_pinmux_rw_pc_iop___pc3___lsb 3 -#define reg_pinmux_rw_pc_iop___pc3___width 1 -#define reg_pinmux_rw_pc_iop___pc3___bit 3 -#define reg_pinmux_rw_pc_iop___pc4___lsb 4 -#define reg_pinmux_rw_pc_iop___pc4___width 1 -#define reg_pinmux_rw_pc_iop___pc4___bit 4 -#define reg_pinmux_rw_pc_iop___pc5___lsb 5 -#define reg_pinmux_rw_pc_iop___pc5___width 1 -#define reg_pinmux_rw_pc_iop___pc5___bit 5 -#define reg_pinmux_rw_pc_iop___pc6___lsb 6 -#define reg_pinmux_rw_pc_iop___pc6___width 1 -#define reg_pinmux_rw_pc_iop___pc6___bit 6 -#define reg_pinmux_rw_pc_iop___pc7___lsb 7 -#define reg_pinmux_rw_pc_iop___pc7___width 1 -#define reg_pinmux_rw_pc_iop___pc7___bit 7 -#define reg_pinmux_rw_pc_iop___pc8___lsb 8 -#define reg_pinmux_rw_pc_iop___pc8___width 1 -#define reg_pinmux_rw_pc_iop___pc8___bit 8 -#define reg_pinmux_rw_pc_iop___pc9___lsb 9 -#define reg_pinmux_rw_pc_iop___pc9___width 1 -#define reg_pinmux_rw_pc_iop___pc9___bit 9 -#define reg_pinmux_rw_pc_iop___pc10___lsb 10 -#define reg_pinmux_rw_pc_iop___pc10___width 1 -#define reg_pinmux_rw_pc_iop___pc10___bit 10 -#define reg_pinmux_rw_pc_iop___pc11___lsb 11 -#define reg_pinmux_rw_pc_iop___pc11___width 1 -#define reg_pinmux_rw_pc_iop___pc11___bit 11 -#define reg_pinmux_rw_pc_iop___pc12___lsb 12 -#define reg_pinmux_rw_pc_iop___pc12___width 1 -#define reg_pinmux_rw_pc_iop___pc12___bit 12 -#define reg_pinmux_rw_pc_iop___pc13___lsb 13 -#define reg_pinmux_rw_pc_iop___pc13___width 1 -#define reg_pinmux_rw_pc_iop___pc13___bit 13 -#define reg_pinmux_rw_pc_iop___pc14___lsb 14 -#define reg_pinmux_rw_pc_iop___pc14___width 1 -#define reg_pinmux_rw_pc_iop___pc14___bit 14 -#define reg_pinmux_rw_pc_iop___pc15___lsb 15 -#define reg_pinmux_rw_pc_iop___pc15___width 1 -#define reg_pinmux_rw_pc_iop___pc15___bit 15 -#define reg_pinmux_rw_pc_iop___pc16___lsb 16 -#define reg_pinmux_rw_pc_iop___pc16___width 1 -#define reg_pinmux_rw_pc_iop___pc16___bit 16 -#define reg_pinmux_rw_pc_iop___pc17___lsb 17 -#define reg_pinmux_rw_pc_iop___pc17___width 1 -#define reg_pinmux_rw_pc_iop___pc17___bit 17 -#define reg_pinmux_rw_pc_iop_offset 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_gio___pd0___lsb 0 -#define reg_pinmux_rw_pd_gio___pd0___width 1 -#define reg_pinmux_rw_pd_gio___pd0___bit 0 -#define reg_pinmux_rw_pd_gio___pd1___lsb 1 -#define reg_pinmux_rw_pd_gio___pd1___width 1 -#define reg_pinmux_rw_pd_gio___pd1___bit 1 -#define reg_pinmux_rw_pd_gio___pd2___lsb 2 -#define reg_pinmux_rw_pd_gio___pd2___width 1 -#define reg_pinmux_rw_pd_gio___pd2___bit 2 -#define reg_pinmux_rw_pd_gio___pd3___lsb 3 -#define reg_pinmux_rw_pd_gio___pd3___width 1 -#define reg_pinmux_rw_pd_gio___pd3___bit 3 -#define reg_pinmux_rw_pd_gio___pd4___lsb 4 -#define reg_pinmux_rw_pd_gio___pd4___width 1 -#define reg_pinmux_rw_pd_gio___pd4___bit 4 -#define reg_pinmux_rw_pd_gio___pd5___lsb 5 -#define reg_pinmux_rw_pd_gio___pd5___width 1 -#define reg_pinmux_rw_pd_gio___pd5___bit 5 -#define reg_pinmux_rw_pd_gio___pd6___lsb 6 -#define reg_pinmux_rw_pd_gio___pd6___width 1 -#define reg_pinmux_rw_pd_gio___pd6___bit 6 -#define reg_pinmux_rw_pd_gio___pd7___lsb 7 -#define reg_pinmux_rw_pd_gio___pd7___width 1 -#define reg_pinmux_rw_pd_gio___pd7___bit 7 -#define reg_pinmux_rw_pd_gio___pd8___lsb 8 -#define reg_pinmux_rw_pd_gio___pd8___width 1 -#define reg_pinmux_rw_pd_gio___pd8___bit 8 -#define reg_pinmux_rw_pd_gio___pd9___lsb 9 -#define reg_pinmux_rw_pd_gio___pd9___width 1 -#define reg_pinmux_rw_pd_gio___pd9___bit 9 -#define reg_pinmux_rw_pd_gio___pd10___lsb 10 -#define reg_pinmux_rw_pd_gio___pd10___width 1 -#define reg_pinmux_rw_pd_gio___pd10___bit 10 -#define reg_pinmux_rw_pd_gio___pd11___lsb 11 -#define reg_pinmux_rw_pd_gio___pd11___width 1 -#define reg_pinmux_rw_pd_gio___pd11___bit 11 -#define reg_pinmux_rw_pd_gio___pd12___lsb 12 -#define reg_pinmux_rw_pd_gio___pd12___width 1 -#define reg_pinmux_rw_pd_gio___pd12___bit 12 -#define reg_pinmux_rw_pd_gio___pd13___lsb 13 -#define reg_pinmux_rw_pd_gio___pd13___width 1 -#define reg_pinmux_rw_pd_gio___pd13___bit 13 -#define reg_pinmux_rw_pd_gio___pd14___lsb 14 -#define reg_pinmux_rw_pd_gio___pd14___width 1 -#define reg_pinmux_rw_pd_gio___pd14___bit 14 -#define reg_pinmux_rw_pd_gio___pd15___lsb 15 -#define reg_pinmux_rw_pd_gio___pd15___width 1 -#define reg_pinmux_rw_pd_gio___pd15___bit 15 -#define reg_pinmux_rw_pd_gio___pd16___lsb 16 -#define reg_pinmux_rw_pd_gio___pd16___width 1 -#define reg_pinmux_rw_pd_gio___pd16___bit 16 -#define reg_pinmux_rw_pd_gio___pd17___lsb 17 -#define reg_pinmux_rw_pd_gio___pd17___width 1 -#define reg_pinmux_rw_pd_gio___pd17___bit 17 -#define reg_pinmux_rw_pd_gio_offset 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pd_iop___pd0___lsb 0 -#define reg_pinmux_rw_pd_iop___pd0___width 1 -#define reg_pinmux_rw_pd_iop___pd0___bit 0 -#define reg_pinmux_rw_pd_iop___pd1___lsb 1 -#define reg_pinmux_rw_pd_iop___pd1___width 1 -#define reg_pinmux_rw_pd_iop___pd1___bit 1 -#define reg_pinmux_rw_pd_iop___pd2___lsb 2 -#define reg_pinmux_rw_pd_iop___pd2___width 1 -#define reg_pinmux_rw_pd_iop___pd2___bit 2 -#define reg_pinmux_rw_pd_iop___pd3___lsb 3 -#define reg_pinmux_rw_pd_iop___pd3___width 1 -#define reg_pinmux_rw_pd_iop___pd3___bit 3 -#define reg_pinmux_rw_pd_iop___pd4___lsb 4 -#define reg_pinmux_rw_pd_iop___pd4___width 1 -#define reg_pinmux_rw_pd_iop___pd4___bit 4 -#define reg_pinmux_rw_pd_iop___pd5___lsb 5 -#define reg_pinmux_rw_pd_iop___pd5___width 1 -#define reg_pinmux_rw_pd_iop___pd5___bit 5 -#define reg_pinmux_rw_pd_iop___pd6___lsb 6 -#define reg_pinmux_rw_pd_iop___pd6___width 1 -#define reg_pinmux_rw_pd_iop___pd6___bit 6 -#define reg_pinmux_rw_pd_iop___pd7___lsb 7 -#define reg_pinmux_rw_pd_iop___pd7___width 1 -#define reg_pinmux_rw_pd_iop___pd7___bit 7 -#define reg_pinmux_rw_pd_iop___pd8___lsb 8 -#define reg_pinmux_rw_pd_iop___pd8___width 1 -#define reg_pinmux_rw_pd_iop___pd8___bit 8 -#define reg_pinmux_rw_pd_iop___pd9___lsb 9 -#define reg_pinmux_rw_pd_iop___pd9___width 1 -#define reg_pinmux_rw_pd_iop___pd9___bit 9 -#define reg_pinmux_rw_pd_iop___pd10___lsb 10 -#define reg_pinmux_rw_pd_iop___pd10___width 1 -#define reg_pinmux_rw_pd_iop___pd10___bit 10 -#define reg_pinmux_rw_pd_iop___pd11___lsb 11 -#define reg_pinmux_rw_pd_iop___pd11___width 1 -#define reg_pinmux_rw_pd_iop___pd11___bit 11 -#define reg_pinmux_rw_pd_iop___pd12___lsb 12 -#define reg_pinmux_rw_pd_iop___pd12___width 1 -#define reg_pinmux_rw_pd_iop___pd12___bit 12 -#define reg_pinmux_rw_pd_iop___pd13___lsb 13 -#define reg_pinmux_rw_pd_iop___pd13___width 1 -#define reg_pinmux_rw_pd_iop___pd13___bit 13 -#define reg_pinmux_rw_pd_iop___pd14___lsb 14 -#define reg_pinmux_rw_pd_iop___pd14___width 1 -#define reg_pinmux_rw_pd_iop___pd14___bit 14 -#define reg_pinmux_rw_pd_iop___pd15___lsb 15 -#define reg_pinmux_rw_pd_iop___pd15___width 1 -#define reg_pinmux_rw_pd_iop___pd15___bit 15 -#define reg_pinmux_rw_pd_iop___pd16___lsb 16 -#define reg_pinmux_rw_pd_iop___pd16___width 1 -#define reg_pinmux_rw_pd_iop___pd16___bit 16 -#define reg_pinmux_rw_pd_iop___pd17___lsb 17 -#define reg_pinmux_rw_pd_iop___pd17___width 1 -#define reg_pinmux_rw_pd_iop___pd17___bit 17 -#define reg_pinmux_rw_pd_iop_offset 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_gio___pe0___lsb 0 -#define reg_pinmux_rw_pe_gio___pe0___width 1 -#define reg_pinmux_rw_pe_gio___pe0___bit 0 -#define reg_pinmux_rw_pe_gio___pe1___lsb 1 -#define reg_pinmux_rw_pe_gio___pe1___width 1 -#define reg_pinmux_rw_pe_gio___pe1___bit 1 -#define reg_pinmux_rw_pe_gio___pe2___lsb 2 -#define reg_pinmux_rw_pe_gio___pe2___width 1 -#define reg_pinmux_rw_pe_gio___pe2___bit 2 -#define reg_pinmux_rw_pe_gio___pe3___lsb 3 -#define reg_pinmux_rw_pe_gio___pe3___width 1 -#define reg_pinmux_rw_pe_gio___pe3___bit 3 -#define reg_pinmux_rw_pe_gio___pe4___lsb 4 -#define reg_pinmux_rw_pe_gio___pe4___width 1 -#define reg_pinmux_rw_pe_gio___pe4___bit 4 -#define reg_pinmux_rw_pe_gio___pe5___lsb 5 -#define reg_pinmux_rw_pe_gio___pe5___width 1 -#define reg_pinmux_rw_pe_gio___pe5___bit 5 -#define reg_pinmux_rw_pe_gio___pe6___lsb 6 -#define reg_pinmux_rw_pe_gio___pe6___width 1 -#define reg_pinmux_rw_pe_gio___pe6___bit 6 -#define reg_pinmux_rw_pe_gio___pe7___lsb 7 -#define reg_pinmux_rw_pe_gio___pe7___width 1 -#define reg_pinmux_rw_pe_gio___pe7___bit 7 -#define reg_pinmux_rw_pe_gio___pe8___lsb 8 -#define reg_pinmux_rw_pe_gio___pe8___width 1 -#define reg_pinmux_rw_pe_gio___pe8___bit 8 -#define reg_pinmux_rw_pe_gio___pe9___lsb 9 -#define reg_pinmux_rw_pe_gio___pe9___width 1 -#define reg_pinmux_rw_pe_gio___pe9___bit 9 -#define reg_pinmux_rw_pe_gio___pe10___lsb 10 -#define reg_pinmux_rw_pe_gio___pe10___width 1 -#define reg_pinmux_rw_pe_gio___pe10___bit 10 -#define reg_pinmux_rw_pe_gio___pe11___lsb 11 -#define reg_pinmux_rw_pe_gio___pe11___width 1 -#define reg_pinmux_rw_pe_gio___pe11___bit 11 -#define reg_pinmux_rw_pe_gio___pe12___lsb 12 -#define reg_pinmux_rw_pe_gio___pe12___width 1 -#define reg_pinmux_rw_pe_gio___pe12___bit 12 -#define reg_pinmux_rw_pe_gio___pe13___lsb 13 -#define reg_pinmux_rw_pe_gio___pe13___width 1 -#define reg_pinmux_rw_pe_gio___pe13___bit 13 -#define reg_pinmux_rw_pe_gio___pe14___lsb 14 -#define reg_pinmux_rw_pe_gio___pe14___width 1 -#define reg_pinmux_rw_pe_gio___pe14___bit 14 -#define reg_pinmux_rw_pe_gio___pe15___lsb 15 -#define reg_pinmux_rw_pe_gio___pe15___width 1 -#define reg_pinmux_rw_pe_gio___pe15___bit 15 -#define reg_pinmux_rw_pe_gio___pe16___lsb 16 -#define reg_pinmux_rw_pe_gio___pe16___width 1 -#define reg_pinmux_rw_pe_gio___pe16___bit 16 -#define reg_pinmux_rw_pe_gio___pe17___lsb 17 -#define reg_pinmux_rw_pe_gio___pe17___width 1 -#define reg_pinmux_rw_pe_gio___pe17___bit 17 -#define reg_pinmux_rw_pe_gio_offset 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -#define reg_pinmux_rw_pe_iop___pe0___lsb 0 -#define reg_pinmux_rw_pe_iop___pe0___width 1 -#define reg_pinmux_rw_pe_iop___pe0___bit 0 -#define reg_pinmux_rw_pe_iop___pe1___lsb 1 -#define reg_pinmux_rw_pe_iop___pe1___width 1 -#define reg_pinmux_rw_pe_iop___pe1___bit 1 -#define reg_pinmux_rw_pe_iop___pe2___lsb 2 -#define reg_pinmux_rw_pe_iop___pe2___width 1 -#define reg_pinmux_rw_pe_iop___pe2___bit 2 -#define reg_pinmux_rw_pe_iop___pe3___lsb 3 -#define reg_pinmux_rw_pe_iop___pe3___width 1 -#define reg_pinmux_rw_pe_iop___pe3___bit 3 -#define reg_pinmux_rw_pe_iop___pe4___lsb 4 -#define reg_pinmux_rw_pe_iop___pe4___width 1 -#define reg_pinmux_rw_pe_iop___pe4___bit 4 -#define reg_pinmux_rw_pe_iop___pe5___lsb 5 -#define reg_pinmux_rw_pe_iop___pe5___width 1 -#define reg_pinmux_rw_pe_iop___pe5___bit 5 -#define reg_pinmux_rw_pe_iop___pe6___lsb 6 -#define reg_pinmux_rw_pe_iop___pe6___width 1 -#define reg_pinmux_rw_pe_iop___pe6___bit 6 -#define reg_pinmux_rw_pe_iop___pe7___lsb 7 -#define reg_pinmux_rw_pe_iop___pe7___width 1 -#define reg_pinmux_rw_pe_iop___pe7___bit 7 -#define reg_pinmux_rw_pe_iop___pe8___lsb 8 -#define reg_pinmux_rw_pe_iop___pe8___width 1 -#define reg_pinmux_rw_pe_iop___pe8___bit 8 -#define reg_pinmux_rw_pe_iop___pe9___lsb 9 -#define reg_pinmux_rw_pe_iop___pe9___width 1 -#define reg_pinmux_rw_pe_iop___pe9___bit 9 -#define reg_pinmux_rw_pe_iop___pe10___lsb 10 -#define reg_pinmux_rw_pe_iop___pe10___width 1 -#define reg_pinmux_rw_pe_iop___pe10___bit 10 -#define reg_pinmux_rw_pe_iop___pe11___lsb 11 -#define reg_pinmux_rw_pe_iop___pe11___width 1 -#define reg_pinmux_rw_pe_iop___pe11___bit 11 -#define reg_pinmux_rw_pe_iop___pe12___lsb 12 -#define reg_pinmux_rw_pe_iop___pe12___width 1 -#define reg_pinmux_rw_pe_iop___pe12___bit 12 -#define reg_pinmux_rw_pe_iop___pe13___lsb 13 -#define reg_pinmux_rw_pe_iop___pe13___width 1 -#define reg_pinmux_rw_pe_iop___pe13___bit 13 -#define reg_pinmux_rw_pe_iop___pe14___lsb 14 -#define reg_pinmux_rw_pe_iop___pe14___width 1 -#define reg_pinmux_rw_pe_iop___pe14___bit 14 -#define reg_pinmux_rw_pe_iop___pe15___lsb 15 -#define reg_pinmux_rw_pe_iop___pe15___width 1 -#define reg_pinmux_rw_pe_iop___pe15___bit 15 -#define reg_pinmux_rw_pe_iop___pe16___lsb 16 -#define reg_pinmux_rw_pe_iop___pe16___width 1 -#define reg_pinmux_rw_pe_iop___pe16___bit 16 -#define reg_pinmux_rw_pe_iop___pe17___lsb 17 -#define reg_pinmux_rw_pe_iop___pe17___width 1 -#define reg_pinmux_rw_pe_iop___pe17___bit 17 -#define reg_pinmux_rw_pe_iop_offset 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -#define reg_pinmux_rw_usb_phy___en_usb0___lsb 0 -#define reg_pinmux_rw_usb_phy___en_usb0___width 1 -#define reg_pinmux_rw_usb_phy___en_usb0___bit 0 -#define reg_pinmux_rw_usb_phy___en_usb1___lsb 1 -#define reg_pinmux_rw_usb_phy___en_usb1___width 1 -#define reg_pinmux_rw_usb_phy___en_usb1___bit 1 -#define reg_pinmux_rw_usb_phy_offset 40 - - -/* Constants */ -#define regk_pinmux_no 0x00000000 -#define regk_pinmux_rw_hwprot_default 0x00000000 -#define regk_pinmux_rw_pa_default 0x00000000 -#define regk_pinmux_rw_pb_gio_default 0x00000000 -#define regk_pinmux_rw_pb_iop_default 0x00000000 -#define regk_pinmux_rw_pc_gio_default 0x00000000 -#define regk_pinmux_rw_pc_iop_default 0x00000000 -#define regk_pinmux_rw_pd_gio_default 0x00000000 -#define regk_pinmux_rw_pd_iop_default 0x00000000 -#define regk_pinmux_rw_pe_gio_default 0x00000000 -#define regk_pinmux_rw_pe_iop_default 0x00000000 -#define regk_pinmux_rw_usb_phy_default 0x00000000 -#define regk_pinmux_yes 0x00000001 -#endif /* __pinmux_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h deleted file mode 100644 index 412b8748e952..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/reg_map_asm.h +++ /dev/null @@ -1,97 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/reg_map_asm.h -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map_asm.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -#define regi_artpec_mod 0xb7044000 -#define regi_ata 0xb0032000 -#define regi_ata_mod 0xb7006000 -#define regi_barber 0xb701a000 -#define regi_bif_core 0xb0014000 -#define regi_bif_dma 0xb0016000 -#define regi_bif_slave 0xb0018000 -#define regi_bif_slave_ext 0xac000000 -#define regi_bus_master 0xb703c000 -#define regi_config 0xb003c000 -#define regi_dma0 0xb0000000 -#define regi_dma1 0xb0002000 -#define regi_dma2 0xb0004000 -#define regi_dma3 0xb0006000 -#define regi_dma4 0xb0008000 -#define regi_dma5 0xb000a000 -#define regi_dma6 0xb000c000 -#define regi_dma7 0xb000e000 -#define regi_dma8 0xb0010000 -#define regi_dma9 0xb0012000 -#define regi_eth0 0xb0034000 -#define regi_eth1 0xb0036000 -#define regi_eth_mod 0xb7004000 -#define regi_eth_mod1 0xb701c000 -#define regi_eth_strmod 0xb7008000 -#define regi_eth_strmod1 0xb7032000 -#define regi_ext_dma 0xb703a000 -#define regi_ext_mem 0xb7046000 -#define regi_gen_io 0xb7016000 -#define regi_gio 0xb001a000 -#define regi_hook 0xb7000000 -#define regi_iop 0xb0020000 -#define regi_irq 0xb001c000 -#define regi_irq_nmi 0xb701e000 -#define regi_marb 0xb003e000 -#define regi_marb_bp0 0xb003e240 -#define regi_marb_bp1 0xb003e280 -#define regi_marb_bp2 0xb003e2c0 -#define regi_marb_bp3 0xb003e300 -#define regi_nand_mod 0xb7014000 -#define regi_p21 0xb002e000 -#define regi_p21_mod 0xb7042000 -#define regi_pci_mod 0xb7010000 -#define regi_pin_test 0xb7018000 -#define regi_pinmux 0xb0038000 -#define regi_sdram_chk 0xb703e000 -#define regi_sdram_mod 0xb7012000 -#define regi_ser0 0xb0026000 -#define regi_ser1 0xb0028000 -#define regi_ser2 0xb002a000 -#define regi_ser3 0xb002c000 -#define regi_ser_mod0 0xb7020000 -#define regi_ser_mod1 0xb7022000 -#define regi_ser_mod2 0xb7024000 -#define regi_ser_mod3 0xb7026000 -#define regi_smif_stat 0xb700e000 -#define regi_sser0 0xb0022000 -#define regi_sser1 0xb0024000 -#define regi_sser_mod0 0xb700a000 -#define regi_sser_mod1 0xb700c000 -#define regi_strcop 0xb0030000 -#define regi_strmux 0xb003a000 -#define regi_strmux_tst 0xb7040000 -#define regi_tap 0xb7002000 -#define regi_timer 0xb001e000 -#define regi_timer_mod 0xb7034000 -#define regi_trace 0xb0040000 -#define regi_usb0 0xb7028000 -#define regi_usb1 0xb702a000 -#define regi_usb2 0xb702c000 -#define regi_usb3 0xb702e000 -#define regi_usb_dev 0xb7030000 -#define regi_utmi_mod0 0xb7036000 -#define regi_utmi_mod1 0xb7038000 -#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h deleted file mode 100644 index 3eb17cfbdc75..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/asm/timer_defs_asm.h +++ /dev/null @@ -1,230 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __timer_defs_asm_h -#define __timer_defs_asm_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -asm --outfile asm/timer_defs_asm.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs_asm.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ - -#ifndef REG_FIELD -#define REG_FIELD( scope, reg, field, value ) \ - REG_FIELD_X_( value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_FIELD_X_( value, shift ) ((value) << shift) -#endif - -#ifndef REG_STATE -#define REG_STATE( scope, reg, field, symbolic_value ) \ - REG_STATE_X_( regk_##scope##_##symbolic_value, reg_##scope##_##reg##___##field##___lsb ) -#define REG_STATE_X_( k, shift ) (k << shift) -#endif - -#ifndef REG_MASK -#define REG_MASK( scope, reg, field ) \ - REG_MASK_X_( reg_##scope##_##reg##___##field##___width, reg_##scope##_##reg##___##field##___lsb ) -#define REG_MASK_X_( width, lsb ) (((1 << width)-1) << lsb) -#endif - -#ifndef REG_LSB -#define REG_LSB( scope, reg, field ) reg_##scope##_##reg##___##field##___lsb -#endif - -#ifndef REG_BIT -#define REG_BIT( scope, reg, field ) reg_##scope##_##reg##___##field##___bit -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) REG_ADDR_X_(inst, reg_##scope##_##reg##_offset) -#define REG_ADDR_X_( inst, offs ) ((inst) + offs) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - REG_ADDR_VECT_X_(inst, reg_##scope##_##reg##_offset, index, \ - STRIDE_##scope##_##reg ) -#define REG_ADDR_VECT_X_( inst, offs, index, stride ) \ - ((inst) + offs + (index) * stride) -#endif - -/* Register rw_tmr0_div, scope timer, type rw */ -#define reg_timer_rw_tmr0_div_offset 0 - -/* Register r_tmr0_data, scope timer, type r */ -#define reg_timer_r_tmr0_data_offset 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr0_ctrl___op___lsb 0 -#define reg_timer_rw_tmr0_ctrl___op___width 2 -#define reg_timer_rw_tmr0_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr0_ctrl___freq___width 3 -#define reg_timer_rw_tmr0_ctrl_offset 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -#define reg_timer_rw_tmr1_div_offset 16 - -/* Register r_tmr1_data, scope timer, type r */ -#define reg_timer_r_tmr1_data_offset 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -#define reg_timer_rw_tmr1_ctrl___op___lsb 0 -#define reg_timer_rw_tmr1_ctrl___op___width 2 -#define reg_timer_rw_tmr1_ctrl___freq___lsb 2 -#define reg_timer_rw_tmr1_ctrl___freq___width 3 -#define reg_timer_rw_tmr1_ctrl_offset 24 - -/* Register rs_cnt_data, scope timer, type rs */ -#define reg_timer_rs_cnt_data___tmr___lsb 0 -#define reg_timer_rs_cnt_data___tmr___width 24 -#define reg_timer_rs_cnt_data___cnt___lsb 24 -#define reg_timer_rs_cnt_data___cnt___width 8 -#define reg_timer_rs_cnt_data_offset 32 - -/* Register r_cnt_data, scope timer, type r */ -#define reg_timer_r_cnt_data___tmr___lsb 0 -#define reg_timer_r_cnt_data___tmr___width 24 -#define reg_timer_r_cnt_data___cnt___lsb 24 -#define reg_timer_r_cnt_data___cnt___width 8 -#define reg_timer_r_cnt_data_offset 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -#define reg_timer_rw_cnt_cfg___clk___lsb 0 -#define reg_timer_rw_cnt_cfg___clk___width 2 -#define reg_timer_rw_cnt_cfg_offset 40 - -/* Register rw_trig, scope timer, type rw */ -#define reg_timer_rw_trig_offset 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -#define reg_timer_rw_trig_cfg___tmr___lsb 0 -#define reg_timer_rw_trig_cfg___tmr___width 2 -#define reg_timer_rw_trig_cfg_offset 52 - -/* Register r_time, scope timer, type r */ -#define reg_timer_r_time_offset 56 - -/* Register rw_out, scope timer, type rw */ -#define reg_timer_rw_out___tmr___lsb 0 -#define reg_timer_rw_out___tmr___width 2 -#define reg_timer_rw_out_offset 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -#define reg_timer_rw_wd_ctrl___cnt___lsb 0 -#define reg_timer_rw_wd_ctrl___cnt___width 8 -#define reg_timer_rw_wd_ctrl___cmd___lsb 8 -#define reg_timer_rw_wd_ctrl___cmd___width 1 -#define reg_timer_rw_wd_ctrl___cmd___bit 8 -#define reg_timer_rw_wd_ctrl___key___lsb 9 -#define reg_timer_rw_wd_ctrl___key___width 7 -#define reg_timer_rw_wd_ctrl_offset 64 - -/* Register r_wd_stat, scope timer, type r */ -#define reg_timer_r_wd_stat___cnt___lsb 0 -#define reg_timer_r_wd_stat___cnt___width 8 -#define reg_timer_r_wd_stat___cmd___lsb 8 -#define reg_timer_r_wd_stat___cmd___width 1 -#define reg_timer_r_wd_stat___cmd___bit 8 -#define reg_timer_r_wd_stat_offset 68 - -/* Register rw_intr_mask, scope timer, type rw */ -#define reg_timer_rw_intr_mask___tmr0___lsb 0 -#define reg_timer_rw_intr_mask___tmr0___width 1 -#define reg_timer_rw_intr_mask___tmr0___bit 0 -#define reg_timer_rw_intr_mask___tmr1___lsb 1 -#define reg_timer_rw_intr_mask___tmr1___width 1 -#define reg_timer_rw_intr_mask___tmr1___bit 1 -#define reg_timer_rw_intr_mask___cnt___lsb 2 -#define reg_timer_rw_intr_mask___cnt___width 1 -#define reg_timer_rw_intr_mask___cnt___bit 2 -#define reg_timer_rw_intr_mask___trig___lsb 3 -#define reg_timer_rw_intr_mask___trig___width 1 -#define reg_timer_rw_intr_mask___trig___bit 3 -#define reg_timer_rw_intr_mask_offset 72 - -/* Register rw_ack_intr, scope timer, type rw */ -#define reg_timer_rw_ack_intr___tmr0___lsb 0 -#define reg_timer_rw_ack_intr___tmr0___width 1 -#define reg_timer_rw_ack_intr___tmr0___bit 0 -#define reg_timer_rw_ack_intr___tmr1___lsb 1 -#define reg_timer_rw_ack_intr___tmr1___width 1 -#define reg_timer_rw_ack_intr___tmr1___bit 1 -#define reg_timer_rw_ack_intr___cnt___lsb 2 -#define reg_timer_rw_ack_intr___cnt___width 1 -#define reg_timer_rw_ack_intr___cnt___bit 2 -#define reg_timer_rw_ack_intr___trig___lsb 3 -#define reg_timer_rw_ack_intr___trig___width 1 -#define reg_timer_rw_ack_intr___trig___bit 3 -#define reg_timer_rw_ack_intr_offset 76 - -/* Register r_intr, scope timer, type r */ -#define reg_timer_r_intr___tmr0___lsb 0 -#define reg_timer_r_intr___tmr0___width 1 -#define reg_timer_r_intr___tmr0___bit 0 -#define reg_timer_r_intr___tmr1___lsb 1 -#define reg_timer_r_intr___tmr1___width 1 -#define reg_timer_r_intr___tmr1___bit 1 -#define reg_timer_r_intr___cnt___lsb 2 -#define reg_timer_r_intr___cnt___width 1 -#define reg_timer_r_intr___cnt___bit 2 -#define reg_timer_r_intr___trig___lsb 3 -#define reg_timer_r_intr___trig___width 1 -#define reg_timer_r_intr___trig___bit 3 -#define reg_timer_r_intr_offset 80 - -/* Register r_masked_intr, scope timer, type r */ -#define reg_timer_r_masked_intr___tmr0___lsb 0 -#define reg_timer_r_masked_intr___tmr0___width 1 -#define reg_timer_r_masked_intr___tmr0___bit 0 -#define reg_timer_r_masked_intr___tmr1___lsb 1 -#define reg_timer_r_masked_intr___tmr1___width 1 -#define reg_timer_r_masked_intr___tmr1___bit 1 -#define reg_timer_r_masked_intr___cnt___lsb 2 -#define reg_timer_r_masked_intr___cnt___width 1 -#define reg_timer_r_masked_intr___cnt___bit 2 -#define reg_timer_r_masked_intr___trig___lsb 3 -#define reg_timer_r_masked_intr___trig___width 1 -#define reg_timer_r_masked_intr___trig___bit 3 -#define reg_timer_r_masked_intr_offset 84 - -/* Register rw_test, scope timer, type rw */ -#define reg_timer_rw_test___dis___lsb 0 -#define reg_timer_rw_test___dis___width 1 -#define reg_timer_rw_test___dis___bit 0 -#define reg_timer_rw_test___en___lsb 1 -#define reg_timer_rw_test___en___width 1 -#define reg_timer_rw_test___en___bit 1 -#define reg_timer_rw_test_offset 88 - - -/* Constants */ -#define regk_timer_ext 0x00000001 -#define regk_timer_f100 0x00000007 -#define regk_timer_f29_493 0x00000004 -#define regk_timer_f32 0x00000005 -#define regk_timer_f32_768 0x00000006 -#define regk_timer_hold 0x00000001 -#define regk_timer_ld 0x00000000 -#define regk_timer_no 0x00000000 -#define regk_timer_off 0x00000000 -#define regk_timer_run 0x00000002 -#define regk_timer_rw_cnt_cfg_default 0x00000000 -#define regk_timer_rw_intr_mask_default 0x00000000 -#define regk_timer_rw_out_default 0x00000000 -#define regk_timer_rw_test_default 0x00000000 -#define regk_timer_rw_tmr0_ctrl_default 0x00000000 -#define regk_timer_rw_tmr1_ctrl_default 0x00000000 -#define regk_timer_rw_trig_cfg_default 0x00000000 -#define regk_timer_start 0x00000001 -#define regk_timer_stop 0x00000000 -#define regk_timer_time 0x00000001 -#define regk_timer_tmr0 0x00000002 -#define regk_timer_tmr1 0x00000003 -#define regk_timer_yes 0x00000001 -#endif /* __timer_defs_asm_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h deleted file mode 100644 index a9ffb7edaf91..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_core_defs.h +++ /dev/null @@ -1,285 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_core_defs_h -#define __bif_core_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_core_regs.r - * id: bif_core_regs.r,v 1.17 2005/02/04 13:28:22 np Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_core_defs.h ../../inst/bif/rtl/bif_core_regs.r - * id: $Id: bif_core_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_core */ - -/* Register rw_grp1_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp1_cfg; -#define REG_RD_ADDR_bif_core_rw_grp1_cfg 0 -#define REG_WR_ADDR_bif_core_rw_grp1_cfg 0 - -/* Register rw_grp2_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 10; -} reg_bif_core_rw_grp2_cfg; -#define REG_RD_ADDR_bif_core_rw_grp2_cfg 4 -#define REG_WR_ADDR_bif_core_rw_grp2_cfg 4 - -/* Register rw_grp3_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 2; - unsigned int gated_csp0 : 2; - unsigned int gated_csp1 : 2; - unsigned int gated_csp2 : 2; - unsigned int gated_csp3 : 2; -} reg_bif_core_rw_grp3_cfg; -#define REG_RD_ADDR_bif_core_rw_grp3_cfg 8 -#define REG_WR_ADDR_bif_core_rw_grp3_cfg 8 - -/* Register rw_grp4_cfg, scope bif_core, type rw */ -typedef struct { - unsigned int lw : 6; - unsigned int ew : 3; - unsigned int zw : 3; - unsigned int aw : 2; - unsigned int dw : 2; - unsigned int ewb : 2; - unsigned int bw : 1; - unsigned int wr_extend : 1; - unsigned int erc_en : 1; - unsigned int mode : 1; - unsigned int dummy1 : 4; - unsigned int gated_csp4 : 2; - unsigned int gated_csp5 : 2; - unsigned int gated_csp6 : 2; -} reg_bif_core_rw_grp4_cfg; -#define REG_RD_ADDR_bif_core_rw_grp4_cfg 12 -#define REG_WR_ADDR_bif_core_rw_grp4_cfg 12 - -/* Register rw_sdram_cfg_grp0, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int grp_sel : 5; - unsigned int dummy1 : 12; -} reg_bif_core_rw_sdram_cfg_grp0; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp0 16 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp0 16 - -/* Register rw_sdram_cfg_grp1, scope bif_core, type rw */ -typedef struct { - unsigned int bank_sel : 5; - unsigned int ca : 3; - unsigned int type : 1; - unsigned int bw : 1; - unsigned int sh : 3; - unsigned int wmm : 1; - unsigned int sh16 : 1; - unsigned int dummy1 : 17; -} reg_bif_core_rw_sdram_cfg_grp1; -#define REG_RD_ADDR_bif_core_rw_sdram_cfg_grp1 20 -#define REG_WR_ADDR_bif_core_rw_sdram_cfg_grp1 20 - -/* Register rw_sdram_timing, scope bif_core, type rw */ -typedef struct { - unsigned int cl : 3; - unsigned int rcd : 3; - unsigned int rp : 3; - unsigned int rc : 2; - unsigned int dpl : 2; - unsigned int pde : 1; - unsigned int ref : 2; - unsigned int cpd : 1; - unsigned int sdcke : 1; - unsigned int sdclk : 1; - unsigned int dummy1 : 13; -} reg_bif_core_rw_sdram_timing; -#define REG_RD_ADDR_bif_core_rw_sdram_timing 24 -#define REG_WR_ADDR_bif_core_rw_sdram_timing 24 - -/* Register rw_sdram_cmd, scope bif_core, type rw */ -typedef struct { - unsigned int cmd : 3; - unsigned int mrs_data : 15; - unsigned int dummy1 : 14; -} reg_bif_core_rw_sdram_cmd; -#define REG_RD_ADDR_bif_core_rw_sdram_cmd 28 -#define REG_WR_ADDR_bif_core_rw_sdram_cmd 28 - -/* Register rs_sdram_ref_stat, scope bif_core, type rs */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_rs_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_rs_sdram_ref_stat 32 - -/* Register r_sdram_ref_stat, scope bif_core, type r */ -typedef struct { - unsigned int ok : 1; - unsigned int dummy1 : 31; -} reg_bif_core_r_sdram_ref_stat; -#define REG_RD_ADDR_bif_core_r_sdram_ref_stat 36 - - -/* Constants */ -enum { - regk_bif_core_bank2 = 0x00000000, - regk_bif_core_bank4 = 0x00000001, - regk_bif_core_bit10 = 0x0000000a, - regk_bif_core_bit11 = 0x0000000b, - regk_bif_core_bit12 = 0x0000000c, - regk_bif_core_bit13 = 0x0000000d, - regk_bif_core_bit14 = 0x0000000e, - regk_bif_core_bit15 = 0x0000000f, - regk_bif_core_bit16 = 0x00000010, - regk_bif_core_bit17 = 0x00000011, - regk_bif_core_bit18 = 0x00000012, - regk_bif_core_bit19 = 0x00000013, - regk_bif_core_bit20 = 0x00000014, - regk_bif_core_bit21 = 0x00000015, - regk_bif_core_bit22 = 0x00000016, - regk_bif_core_bit23 = 0x00000017, - regk_bif_core_bit24 = 0x00000018, - regk_bif_core_bit25 = 0x00000019, - regk_bif_core_bit26 = 0x0000001a, - regk_bif_core_bit27 = 0x0000001b, - regk_bif_core_bit28 = 0x0000001c, - regk_bif_core_bit29 = 0x0000001d, - regk_bif_core_bit9 = 0x00000009, - regk_bif_core_bw16 = 0x00000001, - regk_bif_core_bw32 = 0x00000000, - regk_bif_core_bwe = 0x00000000, - regk_bif_core_cwe = 0x00000001, - regk_bif_core_e15us = 0x00000001, - regk_bif_core_e7800ns = 0x00000002, - regk_bif_core_grp0 = 0x00000000, - regk_bif_core_grp1 = 0x00000001, - regk_bif_core_mrs = 0x00000003, - regk_bif_core_no = 0x00000000, - regk_bif_core_none = 0x00000000, - regk_bif_core_nop = 0x00000000, - regk_bif_core_off = 0x00000000, - regk_bif_core_pre = 0x00000002, - regk_bif_core_r_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rd = 0x00000002, - regk_bif_core_ref = 0x00000001, - regk_bif_core_rs_sdram_ref_stat_default = 0x00000001, - regk_bif_core_rw_grp1_cfg_default = 0x000006cf, - regk_bif_core_rw_grp2_cfg_default = 0x000006cf, - regk_bif_core_rw_grp3_cfg_default = 0x000006cf, - regk_bif_core_rw_grp4_cfg_default = 0x000006cf, - regk_bif_core_rw_sdram_cfg_grp1_default = 0x00000000, - regk_bif_core_slf = 0x00000004, - regk_bif_core_wr = 0x00000001, - regk_bif_core_yes = 0x00000001 -}; -#endif /* __bif_core_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h deleted file mode 100644 index d1fa172f58f4..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_dma_defs.h +++ /dev/null @@ -1,474 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_dma_defs_h -#define __bif_dma_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_dma_regs.r - * id: bif_dma_regs.r,v 1.6 2005/02/04 13:28:31 perz Exp - * last modfied: Mon Apr 11 16:06:33 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_dma_defs.h ../../inst/bif/rtl/bif_dma_regs.r - * id: $Id: bif_dma_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_dma */ - -/* Register rw_ch0_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch0_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch0_ctrl 0 -#define REG_WR_ADDR_bif_dma_rw_ch0_ctrl 0 - -/* Register rw_ch0_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch0_addr; -#define REG_RD_ADDR_bif_dma_rw_ch0_addr 4 -#define REG_WR_ADDR_bif_dma_rw_ch0_addr 4 - -/* Register rw_ch0_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch0_start; -#define REG_RD_ADDR_bif_dma_rw_ch0_start 8 -#define REG_WR_ADDR_bif_dma_rw_ch0_start 8 - -/* Register rw_ch0_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch0_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch0_cnt 12 -#define REG_WR_ADDR_bif_dma_rw_ch0_cnt 12 - -/* Register r_ch0_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch0_stat; -#define REG_RD_ADDR_bif_dma_r_ch0_stat 16 - -/* Register rw_ch1_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch1_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch1_ctrl 32 -#define REG_WR_ADDR_bif_dma_rw_ch1_ctrl 32 - -/* Register rw_ch1_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch1_addr; -#define REG_RD_ADDR_bif_dma_rw_ch1_addr 36 -#define REG_WR_ADDR_bif_dma_rw_ch1_addr 36 - -/* Register rw_ch1_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch1_start; -#define REG_RD_ADDR_bif_dma_rw_ch1_start 40 -#define REG_WR_ADDR_bif_dma_rw_ch1_start 40 - -/* Register rw_ch1_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch1_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch1_cnt 44 -#define REG_WR_ADDR_bif_dma_rw_ch1_cnt 44 - -/* Register r_ch1_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch1_stat; -#define REG_RD_ADDR_bif_dma_r_ch1_stat 48 - -/* Register rw_ch2_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_pad : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int wr_all : 1; - unsigned int dummy1 : 12; -} reg_bif_dma_rw_ch2_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch2_ctrl 64 -#define REG_WR_ADDR_bif_dma_rw_ch2_ctrl 64 - -/* Register rw_ch2_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch2_addr; -#define REG_RD_ADDR_bif_dma_rw_ch2_addr 68 -#define REG_WR_ADDR_bif_dma_rw_ch2_addr 68 - -/* Register rw_ch2_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch2_start; -#define REG_RD_ADDR_bif_dma_rw_ch2_start 72 -#define REG_WR_ADDR_bif_dma_rw_ch2_start 72 - -/* Register rw_ch2_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch2_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch2_cnt 76 -#define REG_WR_ADDR_bif_dma_rw_ch2_cnt 76 - -/* Register r_ch2_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch2_stat; -#define REG_RD_ADDR_bif_dma_r_ch2_stat 80 - -/* Register rw_ch3_ctrl, scope bif_dma, type rw */ -typedef struct { - unsigned int bw : 2; - unsigned int burst_len : 1; - unsigned int cont : 1; - unsigned int end_discard : 1; - unsigned int cnt : 1; - unsigned int dreq_pin : 3; - unsigned int dreq_mode : 2; - unsigned int tc_in_pin : 3; - unsigned int tc_in_mode : 2; - unsigned int bus_mode : 2; - unsigned int rate_en : 1; - unsigned int dummy1 : 13; -} reg_bif_dma_rw_ch3_ctrl; -#define REG_RD_ADDR_bif_dma_rw_ch3_ctrl 96 -#define REG_WR_ADDR_bif_dma_rw_ch3_ctrl 96 - -/* Register rw_ch3_addr, scope bif_dma, type rw */ -typedef struct { - unsigned int addr : 32; -} reg_bif_dma_rw_ch3_addr; -#define REG_RD_ADDR_bif_dma_rw_ch3_addr 100 -#define REG_WR_ADDR_bif_dma_rw_ch3_addr 100 - -/* Register rw_ch3_start, scope bif_dma, type rw */ -typedef struct { - unsigned int run : 1; - unsigned int dummy1 : 31; -} reg_bif_dma_rw_ch3_start; -#define REG_RD_ADDR_bif_dma_rw_ch3_start 104 -#define REG_WR_ADDR_bif_dma_rw_ch3_start 104 - -/* Register rw_ch3_cnt, scope bif_dma, type rw */ -typedef struct { - unsigned int start_cnt : 16; - unsigned int dummy1 : 16; -} reg_bif_dma_rw_ch3_cnt; -#define REG_RD_ADDR_bif_dma_rw_ch3_cnt 108 -#define REG_WR_ADDR_bif_dma_rw_ch3_cnt 108 - -/* Register r_ch3_stat, scope bif_dma, type r */ -typedef struct { - unsigned int cnt : 16; - unsigned int dummy1 : 15; - unsigned int run : 1; -} reg_bif_dma_r_ch3_stat; -#define REG_RD_ADDR_bif_dma_r_ch3_stat 112 - -/* Register rw_intr_mask, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_intr_mask; -#define REG_RD_ADDR_bif_dma_rw_intr_mask 128 -#define REG_WR_ADDR_bif_dma_rw_intr_mask 128 - -/* Register rw_ack_intr, scope bif_dma, type rw */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_rw_ack_intr; -#define REG_RD_ADDR_bif_dma_rw_ack_intr 132 -#define REG_WR_ADDR_bif_dma_rw_ack_intr 132 - -/* Register r_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_intr; -#define REG_RD_ADDR_bif_dma_r_intr 136 - -/* Register r_masked_intr, scope bif_dma, type r */ -typedef struct { - unsigned int ext_dma0 : 1; - unsigned int ext_dma1 : 1; - unsigned int ext_dma2 : 1; - unsigned int ext_dma3 : 1; - unsigned int dummy1 : 28; -} reg_bif_dma_r_masked_intr; -#define REG_RD_ADDR_bif_dma_r_masked_intr 140 - -/* Register rw_pin0_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin0_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin0_cfg 160 -#define REG_WR_ADDR_bif_dma_rw_pin0_cfg 160 - -/* Register rw_pin1_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin1_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin1_cfg 164 -#define REG_WR_ADDR_bif_dma_rw_pin1_cfg 164 - -/* Register rw_pin2_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin2_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin2_cfg 168 -#define REG_WR_ADDR_bif_dma_rw_pin2_cfg 168 - -/* Register rw_pin3_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin3_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin3_cfg 172 -#define REG_WR_ADDR_bif_dma_rw_pin3_cfg 172 - -/* Register rw_pin4_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin4_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin4_cfg 176 -#define REG_WR_ADDR_bif_dma_rw_pin4_cfg 176 - -/* Register rw_pin5_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin5_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin5_cfg 180 -#define REG_WR_ADDR_bif_dma_rw_pin5_cfg 180 - -/* Register rw_pin6_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin6_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin6_cfg 184 -#define REG_WR_ADDR_bif_dma_rw_pin6_cfg 184 - -/* Register rw_pin7_cfg, scope bif_dma, type rw */ -typedef struct { - unsigned int master_ch : 2; - unsigned int master_mode : 3; - unsigned int slave_ch : 2; - unsigned int slave_mode : 3; - unsigned int dummy1 : 22; -} reg_bif_dma_rw_pin7_cfg; -#define REG_RD_ADDR_bif_dma_rw_pin7_cfg 188 -#define REG_WR_ADDR_bif_dma_rw_pin7_cfg 188 - -/* Register r_pin_stat, scope bif_dma, type r */ -typedef struct { - unsigned int pin0 : 1; - unsigned int pin1 : 1; - unsigned int pin2 : 1; - unsigned int pin3 : 1; - unsigned int pin4 : 1; - unsigned int pin5 : 1; - unsigned int pin6 : 1; - unsigned int pin7 : 1; - unsigned int dummy1 : 24; -} reg_bif_dma_r_pin_stat; -#define REG_RD_ADDR_bif_dma_r_pin_stat 192 - - -/* Constants */ -enum { - regk_bif_dma_as_master = 0x00000001, - regk_bif_dma_as_slave = 0x00000001, - regk_bif_dma_burst1 = 0x00000000, - regk_bif_dma_burst8 = 0x00000001, - regk_bif_dma_bw16 = 0x00000001, - regk_bif_dma_bw32 = 0x00000002, - regk_bif_dma_bw8 = 0x00000000, - regk_bif_dma_dack = 0x00000006, - regk_bif_dma_dack_inv = 0x00000007, - regk_bif_dma_force = 0x00000001, - regk_bif_dma_hi = 0x00000003, - regk_bif_dma_inv = 0x00000003, - regk_bif_dma_lo = 0x00000002, - regk_bif_dma_master = 0x00000001, - regk_bif_dma_no = 0x00000000, - regk_bif_dma_norm = 0x00000002, - regk_bif_dma_off = 0x00000000, - regk_bif_dma_rw_ch0_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch0_start_default = 0x00000000, - regk_bif_dma_rw_ch1_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch1_start_default = 0x00000000, - regk_bif_dma_rw_ch2_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch2_start_default = 0x00000000, - regk_bif_dma_rw_ch3_ctrl_default = 0x00000000, - regk_bif_dma_rw_ch3_start_default = 0x00000000, - regk_bif_dma_rw_intr_mask_default = 0x00000000, - regk_bif_dma_rw_pin0_cfg_default = 0x00000000, - regk_bif_dma_rw_pin1_cfg_default = 0x00000000, - regk_bif_dma_rw_pin2_cfg_default = 0x00000000, - regk_bif_dma_rw_pin3_cfg_default = 0x00000000, - regk_bif_dma_rw_pin4_cfg_default = 0x00000000, - regk_bif_dma_rw_pin5_cfg_default = 0x00000000, - regk_bif_dma_rw_pin6_cfg_default = 0x00000000, - regk_bif_dma_rw_pin7_cfg_default = 0x00000000, - regk_bif_dma_slave = 0x00000002, - regk_bif_dma_sreq = 0x00000006, - regk_bif_dma_sreq_inv = 0x00000007, - regk_bif_dma_tc = 0x00000004, - regk_bif_dma_tc_inv = 0x00000005, - regk_bif_dma_yes = 0x00000001 -}; -#endif /* __bif_dma_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h deleted file mode 100644 index a8d7cc528546..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/bif_slave_defs.h +++ /dev/null @@ -1,250 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __bif_slave_defs_h -#define __bif_slave_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/bif/rtl/bif_slave_regs.r - * id: bif_slave_regs.r,v 1.5 2005/02/04 13:55:28 perz Exp - * last modfied: Mon Apr 11 16:06:34 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile bif_slave_defs.h ../../inst/bif/rtl/bif_slave_regs.r - * id: $Id: bif_slave_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope bif_slave */ - -/* Register rw_slave_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int slave_id : 3; - unsigned int use_slave_id : 1; - unsigned int boot_rdy : 1; - unsigned int loopback : 1; - unsigned int dis : 1; - unsigned int dummy1 : 25; -} reg_bif_slave_rw_slave_cfg; -#define REG_RD_ADDR_bif_slave_rw_slave_cfg 0 -#define REG_WR_ADDR_bif_slave_rw_slave_cfg 0 - -/* Register r_slave_mode, scope bif_slave, type r */ -typedef struct { - unsigned int ch0_mode : 1; - unsigned int ch1_mode : 1; - unsigned int ch2_mode : 1; - unsigned int ch3_mode : 1; - unsigned int dummy1 : 28; -} reg_bif_slave_r_slave_mode; -#define REG_RD_ADDR_bif_slave_r_slave_mode 4 - -/* Register rw_ch0_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch0_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch0_cfg 16 -#define REG_WR_ADDR_bif_slave_rw_ch0_cfg 16 - -/* Register rw_ch1_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch1_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch1_cfg 20 -#define REG_WR_ADDR_bif_slave_rw_ch1_cfg 20 - -/* Register rw_ch2_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch2_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch2_cfg 24 -#define REG_WR_ADDR_bif_slave_rw_ch2_cfg 24 - -/* Register rw_ch3_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int rd_hold : 2; - unsigned int access_mode : 1; - unsigned int access_ctrl : 1; - unsigned int data_cs : 2; - unsigned int dummy1 : 26; -} reg_bif_slave_rw_ch3_cfg; -#define REG_RD_ADDR_bif_slave_rw_ch3_cfg 28 -#define REG_WR_ADDR_bif_slave_rw_ch3_cfg 28 - -/* Register rw_arb_cfg, scope bif_slave, type rw */ -typedef struct { - unsigned int brin_mode : 1; - unsigned int brout_mode : 3; - unsigned int bg_mode : 3; - unsigned int release : 2; - unsigned int acquire : 1; - unsigned int settle_time : 2; - unsigned int dram_ctrl : 1; - unsigned int dummy1 : 19; -} reg_bif_slave_rw_arb_cfg; -#define REG_RD_ADDR_bif_slave_rw_arb_cfg 32 -#define REG_WR_ADDR_bif_slave_rw_arb_cfg 32 - -/* Register r_arb_stat, scope bif_slave, type r */ -typedef struct { - unsigned int init_mode : 1; - unsigned int mode : 1; - unsigned int brin : 1; - unsigned int brout : 1; - unsigned int bg : 1; - unsigned int dummy1 : 27; -} reg_bif_slave_r_arb_stat; -#define REG_RD_ADDR_bif_slave_r_arb_stat 36 - -/* Register rw_intr_mask, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_intr_mask; -#define REG_RD_ADDR_bif_slave_rw_intr_mask 64 -#define REG_WR_ADDR_bif_slave_rw_intr_mask 64 - -/* Register rw_ack_intr, scope bif_slave, type rw */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_rw_ack_intr; -#define REG_RD_ADDR_bif_slave_rw_ack_intr 68 -#define REG_WR_ADDR_bif_slave_rw_ack_intr 68 - -/* Register r_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_intr; -#define REG_RD_ADDR_bif_slave_r_intr 72 - -/* Register r_masked_intr, scope bif_slave, type r */ -typedef struct { - unsigned int bus_release : 1; - unsigned int bus_acquire : 1; - unsigned int dummy1 : 30; -} reg_bif_slave_r_masked_intr; -#define REG_RD_ADDR_bif_slave_r_masked_intr 76 - - -/* Constants */ -enum { - regk_bif_slave_active_hi = 0x00000003, - regk_bif_slave_active_lo = 0x00000002, - regk_bif_slave_addr = 0x00000000, - regk_bif_slave_always = 0x00000001, - regk_bif_slave_at_idle = 0x00000002, - regk_bif_slave_burst_end = 0x00000003, - regk_bif_slave_dma = 0x00000001, - regk_bif_slave_hi = 0x00000003, - regk_bif_slave_inv = 0x00000001, - regk_bif_slave_lo = 0x00000002, - regk_bif_slave_local = 0x00000001, - regk_bif_slave_master = 0x00000000, - regk_bif_slave_mode_reg = 0x00000001, - regk_bif_slave_no = 0x00000000, - regk_bif_slave_norm = 0x00000000, - regk_bif_slave_on_access = 0x00000000, - regk_bif_slave_rw_arb_cfg_default = 0x00000000, - regk_bif_slave_rw_ch0_cfg_default = 0x00000000, - regk_bif_slave_rw_ch1_cfg_default = 0x00000000, - regk_bif_slave_rw_ch2_cfg_default = 0x00000000, - regk_bif_slave_rw_ch3_cfg_default = 0x00000000, - regk_bif_slave_rw_intr_mask_default = 0x00000000, - regk_bif_slave_rw_slave_cfg_default = 0x00000000, - regk_bif_slave_shared = 0x00000000, - regk_bif_slave_slave = 0x00000001, - regk_bif_slave_t0ns = 0x00000003, - regk_bif_slave_t10ns = 0x00000002, - regk_bif_slave_t20ns = 0x00000003, - regk_bif_slave_t30ns = 0x00000002, - regk_bif_slave_t40ns = 0x00000001, - regk_bif_slave_t50ns = 0x00000000, - regk_bif_slave_yes = 0x00000001, - regk_bif_slave_z = 0x00000004 -}; -#endif /* __bif_slave_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h deleted file mode 100644 index cc8b20d17237..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/config_defs.h +++ /dev/null @@ -1,143 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __config_defs_h -#define __config_defs_h - -/* - * This file is autogenerated from - * file: ../../rtl/config_regs.r - * id: config_regs.r,v 1.23 2004/03/04 11:34:42 mikaeln Exp - * last modfied: Thu Mar 4 12:34:39 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile config_defs.h ../../rtl/config_regs.r - * id: $Id: config_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope config */ - -/* Register r_bootsel, scope config, type r */ -typedef struct { - unsigned int boot_mode : 3; - unsigned int full_duplex : 1; - unsigned int user : 1; - unsigned int pll : 1; - unsigned int flash_bw : 1; - unsigned int dummy1 : 25; -} reg_config_r_bootsel; -#define REG_RD_ADDR_config_r_bootsel 0 - -/* Register rw_clk_ctrl, scope config, type rw */ -typedef struct { - unsigned int pll : 1; - unsigned int cpu : 1; - unsigned int iop : 1; - unsigned int dma01_eth0 : 1; - unsigned int dma23 : 1; - unsigned int dma45 : 1; - unsigned int dma67 : 1; - unsigned int dma89_strcop : 1; - unsigned int bif : 1; - unsigned int fix_io : 1; - unsigned int dummy1 : 22; -} reg_config_rw_clk_ctrl; -#define REG_RD_ADDR_config_rw_clk_ctrl 4 -#define REG_WR_ADDR_config_rw_clk_ctrl 4 - -/* Register rw_pad_ctrl, scope config, type rw */ -typedef struct { - unsigned int usb_susp : 1; - unsigned int phyrst_n : 1; - unsigned int dummy1 : 30; -} reg_config_rw_pad_ctrl; -#define REG_RD_ADDR_config_rw_pad_ctrl 8 -#define REG_WR_ADDR_config_rw_pad_ctrl 8 - - -/* Constants */ -enum { - regk_config_bw16 = 0x00000000, - regk_config_bw32 = 0x00000001, - regk_config_master = 0x00000005, - regk_config_nand = 0x00000003, - regk_config_net_rx = 0x00000001, - regk_config_net_tx_rx = 0x00000002, - regk_config_no = 0x00000000, - regk_config_none = 0x00000007, - regk_config_nor = 0x00000000, - regk_config_rw_clk_ctrl_default = 0x00000002, - regk_config_rw_pad_ctrl_default = 0x00000000, - regk_config_ser = 0x00000004, - regk_config_slave = 0x00000006, - regk_config_yes = 0x00000001 -}; -#endif /* __config_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h deleted file mode 100644 index da0b1103b66d..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/gio_defs.h +++ /dev/null @@ -1,296 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __gio_defs_h -#define __gio_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/gio/rtl/gio_regs.r - * id: gio_regs.r,v 1.5 2005/02/04 09:43:21 perz Exp - * last modfied: Mon Apr 11 16:07:47 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile gio_defs.h ../../inst/gio/rtl/gio_regs.r - * id: $Id: gio_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope gio */ - -/* Register rw_pa_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_dout; -#define REG_RD_ADDR_gio_rw_pa_dout 0 -#define REG_WR_ADDR_gio_rw_pa_dout 0 - -/* Register r_pa_din, scope gio, type r */ -typedef struct { - unsigned int data : 8; - unsigned int dummy1 : 24; -} reg_gio_r_pa_din; -#define REG_RD_ADDR_gio_r_pa_din 4 - -/* Register rw_pa_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 8; - unsigned int dummy1 : 24; -} reg_gio_rw_pa_oe; -#define REG_RD_ADDR_gio_rw_pa_oe 8 -#define REG_WR_ADDR_gio_rw_pa_oe 8 - -/* Register rw_intr_cfg, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 3; - unsigned int pa1 : 3; - unsigned int pa2 : 3; - unsigned int pa3 : 3; - unsigned int pa4 : 3; - unsigned int pa5 : 3; - unsigned int pa6 : 3; - unsigned int pa7 : 3; - unsigned int dummy1 : 8; -} reg_gio_rw_intr_cfg; -#define REG_RD_ADDR_gio_rw_intr_cfg 12 -#define REG_WR_ADDR_gio_rw_intr_cfg 12 - -/* Register rw_intr_mask, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_intr_mask; -#define REG_RD_ADDR_gio_rw_intr_mask 16 -#define REG_WR_ADDR_gio_rw_intr_mask 16 - -/* Register rw_ack_intr, scope gio, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_rw_ack_intr; -#define REG_RD_ADDR_gio_rw_ack_intr 20 -#define REG_WR_ADDR_gio_rw_ack_intr 20 - -/* Register r_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_intr; -#define REG_RD_ADDR_gio_r_intr 24 - -/* Register r_masked_intr, scope gio, type r */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int dummy1 : 24; -} reg_gio_r_masked_intr; -#define REG_RD_ADDR_gio_r_masked_intr 28 - -/* Register rw_pb_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_dout; -#define REG_RD_ADDR_gio_rw_pb_dout 32 -#define REG_WR_ADDR_gio_rw_pb_dout 32 - -/* Register r_pb_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pb_din; -#define REG_RD_ADDR_gio_r_pb_din 36 - -/* Register rw_pb_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pb_oe; -#define REG_RD_ADDR_gio_rw_pb_oe 40 -#define REG_WR_ADDR_gio_rw_pb_oe 40 - -/* Register rw_pc_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_dout; -#define REG_RD_ADDR_gio_rw_pc_dout 48 -#define REG_WR_ADDR_gio_rw_pc_dout 48 - -/* Register r_pc_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pc_din; -#define REG_RD_ADDR_gio_r_pc_din 52 - -/* Register rw_pc_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pc_oe; -#define REG_RD_ADDR_gio_rw_pc_oe 56 -#define REG_WR_ADDR_gio_rw_pc_oe 56 - -/* Register rw_pd_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_dout; -#define REG_RD_ADDR_gio_rw_pd_dout 64 -#define REG_WR_ADDR_gio_rw_pd_dout 64 - -/* Register r_pd_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pd_din; -#define REG_RD_ADDR_gio_r_pd_din 68 - -/* Register rw_pd_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pd_oe; -#define REG_RD_ADDR_gio_rw_pd_oe 72 -#define REG_WR_ADDR_gio_rw_pd_oe 72 - -/* Register rw_pe_dout, scope gio, type rw */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_dout; -#define REG_RD_ADDR_gio_rw_pe_dout 80 -#define REG_WR_ADDR_gio_rw_pe_dout 80 - -/* Register r_pe_din, scope gio, type r */ -typedef struct { - unsigned int data : 18; - unsigned int dummy1 : 14; -} reg_gio_r_pe_din; -#define REG_RD_ADDR_gio_r_pe_din 84 - -/* Register rw_pe_oe, scope gio, type rw */ -typedef struct { - unsigned int oe : 18; - unsigned int dummy1 : 14; -} reg_gio_rw_pe_oe; -#define REG_RD_ADDR_gio_rw_pe_oe 88 -#define REG_WR_ADDR_gio_rw_pe_oe 88 - - -/* Constants */ -enum { - regk_gio_anyedge = 0x00000007, - regk_gio_hi = 0x00000001, - regk_gio_lo = 0x00000002, - regk_gio_negedge = 0x00000006, - regk_gio_no = 0x00000000, - regk_gio_off = 0x00000000, - regk_gio_posedge = 0x00000005, - regk_gio_rw_intr_cfg_default = 0x00000000, - regk_gio_rw_intr_mask_default = 0x00000000, - regk_gio_rw_pa_oe_default = 0x00000000, - regk_gio_rw_pb_oe_default = 0x00000000, - regk_gio_rw_pc_oe_default = 0x00000000, - regk_gio_rw_pd_oe_default = 0x00000000, - regk_gio_rw_pe_oe_default = 0x00000000, - regk_gio_set = 0x00000003, - regk_gio_yes = 0x00000001 -}; -#endif /* __gio_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h deleted file mode 100644 index ea752a2d8ee2..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect.h +++ /dev/null @@ -1,42 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Interrupt vector numbers autogenerated by /n/asic/design/tools/rdesc/src/rdes2intr version - from ../../inst/intr_vect/rtl/guinness/ivmask.config.r -version . */ - -#ifndef _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define _______INST_INTR_VECT_RTL_GUINNESS_IVMASK_CONFIG_R -#define MEMARB_INTR_VECT 0x31 -#define GEN_IO_INTR_VECT 0x32 -#define GIO_INTR_VECT GEN_IO_INTR_VECT -#define IOP0_INTR_VECT 0x33 -#define IOP1_INTR_VECT 0x34 -#define IOP2_INTR_VECT 0x35 -#define IOP3_INTR_VECT 0x36 -#define DMA0_INTR_VECT 0x37 -#define DMA1_INTR_VECT 0x38 -#define DMA2_INTR_VECT 0x39 -#define DMA3_INTR_VECT 0x3a -#define DMA4_INTR_VECT 0x3b -#define DMA5_INTR_VECT 0x3c -#define DMA6_INTR_VECT 0x3d -#define DMA7_INTR_VECT 0x3e -#define DMA8_INTR_VECT 0x3f -#define DMA9_INTR_VECT 0x40 -#define ATA_INTR_VECT 0x41 -#define SSER0_INTR_VECT 0x42 -#define SSER1_INTR_VECT 0x43 -#define SER0_INTR_VECT 0x44 -#define SER1_INTR_VECT 0x45 -#define SER2_INTR_VECT 0x46 -#define SER3_INTR_VECT 0x47 -#define P21_INTR_VECT 0x48 -#define ETH0_INTR_VECT 0x49 -#define ETH1_INTR_VECT 0x4a -#define TIMER_INTR_VECT 0x4b -#define TIMER0_INTR_VECT TIMER_INTR_VECT -#define BIF_ARB_INTR_VECT 0x4c -#define BIF_DMA_INTR_VECT 0x4d -#define EXT_INTR_VECT 0x4e -#define IPI_INTR_VECT 0x4f -#define NBR_INTR_VECT 0x50 -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h deleted file mode 100644 index 11ebd66585cd..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/intr_vect_defs.h +++ /dev/null @@ -1,229 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __intr_vect_defs_h -#define __intr_vect_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: ivmask.config.r,v 1.4 2005/02/15 16:05:38 stefans Exp - * last modfied: Mon Apr 11 16:08:03 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile intr_vect_defs.h ../../inst/intr_vect/rtl/guinness/ivmask.config.r - * id: $Id: intr_vect_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope intr_vect */ - -#define STRIDE_intr_vect_rw_mask 0 -/* Register rw_mask, scope intr_vect, type rw */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer0 : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_rw_mask; -#define REG_RD_ADDR_intr_vect_rw_mask 0 -#define REG_WR_ADDR_intr_vect_rw_mask 0 - -#define STRIDE_intr_vect_r_vect 0 -/* Register r_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_vect; -#define REG_RD_ADDR_intr_vect_r_vect 4 - -#define STRIDE_intr_vect_r_masked_vect 0 -/* Register r_masked_vect, scope intr_vect, type r */ -typedef struct { - unsigned int memarb : 1; - unsigned int gen_io : 1; - unsigned int iop0 : 1; - unsigned int iop1 : 1; - unsigned int iop2 : 1; - unsigned int iop3 : 1; - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int ata : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ser0 : 1; - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int p21 : 1; - unsigned int eth0 : 1; - unsigned int eth1 : 1; - unsigned int timer : 1; - unsigned int bif_arb : 1; - unsigned int bif_dma : 1; - unsigned int ext : 1; - unsigned int dummy1 : 2; -} reg_intr_vect_r_masked_vect; -#define REG_RD_ADDR_intr_vect_r_masked_vect 8 - -/* Register r_nmi, scope intr_vect, type r */ -typedef struct { - unsigned int ext : 1; - unsigned int watchdog : 1; - unsigned int dummy1 : 30; -} reg_intr_vect_r_nmi; -#define REG_RD_ADDR_intr_vect_r_nmi 12 - -/* Register r_guru, scope intr_vect, type r */ -typedef struct { - unsigned int jtag : 1; - unsigned int dummy1 : 31; -} reg_intr_vect_r_guru; -#define REG_RD_ADDR_intr_vect_r_guru 16 - -/* Register rw_ipi, scope intr_vect, type rw */ -typedef struct -{ - unsigned int vector; -} reg_intr_vect_rw_ipi; -#define REG_RD_ADDR_intr_vect_rw_ipi 20 -#define REG_WR_ADDR_intr_vect_rw_ipi 20 - -/* Constants */ -enum { - regk_intr_vect_off = 0x00000000, - regk_intr_vect_on = 0x00000001, - regk_intr_vect_rw_mask_default = 0x00000000 -}; -#endif /* __intr_vect_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h deleted file mode 100644 index fb7e20d77591..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_bp_defs.h +++ /dev/null @@ -1,206 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Fri Nov 7 15:36:04 2003 - * - * by /n/asic/projects/guinness/design/top/inst/rdesc/rdes2c ../../rtl/global.rmap ../../mod/modreg.rmap -base 0xb0000000 ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_bp_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_break_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_addr; -#define REG_RD_ADDR_marb_bp_r_break_addr 20 - -/* Register r_break_op, scope marb_bp, type r */ -typedef struct { - unsigned int read : 1; - unsigned int write : 1; - unsigned int read_excl : 1; - unsigned int pri_write : 1; - unsigned int us_read : 1; - unsigned int us_write : 1; - unsigned int us_read_excl : 1; - unsigned int us_pri_write : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_break_op; -#define REG_RD_ADDR_marb_bp_r_break_op 24 - -/* Register r_break_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_clients; -#define REG_RD_ADDR_marb_bp_r_break_clients 28 - -/* Register r_break_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_break_first_client; -#define REG_RD_ADDR_marb_bp_r_break_first_client 32 - -/* Register r_break_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_break_size; -#define REG_RD_ADDR_marb_bp_r_break_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h deleted file mode 100644 index 872a7942916a..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/marb_defs.h +++ /dev/null @@ -1,476 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __marb_defs_h -#define __marb_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb */ - -#define STRIDE_marb_rw_int_slots 4 -/* Register rw_int_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_int_slots; -#define REG_RD_ADDR_marb_rw_int_slots 0 -#define REG_WR_ADDR_marb_rw_int_slots 0 - -#define STRIDE_marb_rw_ext_slots 4 -/* Register rw_ext_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_ext_slots; -#define REG_RD_ADDR_marb_rw_ext_slots 256 -#define REG_WR_ADDR_marb_rw_ext_slots 256 - -#define STRIDE_marb_rw_regs_slots 4 -/* Register rw_regs_slots, scope marb, type rw */ -typedef struct { - unsigned int owner : 4; - unsigned int dummy1 : 28; -} reg_marb_rw_regs_slots; -#define REG_RD_ADDR_marb_rw_regs_slots 512 -#define REG_WR_ADDR_marb_rw_regs_slots 512 - -/* Register rw_intr_mask, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_intr_mask; -#define REG_RD_ADDR_marb_rw_intr_mask 528 -#define REG_WR_ADDR_marb_rw_intr_mask 528 - -/* Register rw_ack_intr, scope marb, type rw */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_rw_ack_intr; -#define REG_RD_ADDR_marb_rw_ack_intr 532 -#define REG_WR_ADDR_marb_rw_ack_intr 532 - -/* Register r_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_intr; -#define REG_RD_ADDR_marb_r_intr 536 - -/* Register r_masked_intr, scope marb, type r */ -typedef struct { - unsigned int bp0 : 1; - unsigned int bp1 : 1; - unsigned int bp2 : 1; - unsigned int bp3 : 1; - unsigned int dummy1 : 28; -} reg_marb_r_masked_intr; -#define REG_RD_ADDR_marb_r_masked_intr 540 - -/* Register rw_stop_mask, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_stop_mask; -#define REG_RD_ADDR_marb_rw_stop_mask 544 -#define REG_WR_ADDR_marb_rw_stop_mask 544 - -/* Register r_stopped, scope marb, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_r_stopped; -#define REG_RD_ADDR_marb_r_stopped 548 - -/* Register rw_no_snoop, scope marb, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_rw_no_snoop; -#define REG_RD_ADDR_marb_rw_no_snoop 832 -#define REG_WR_ADDR_marb_rw_no_snoop 832 - -/* Register rw_no_snoop_rq, scope marb, type rw */ -typedef struct { - unsigned int dummy1 : 10; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int dummy2 : 20; -} reg_marb_rw_no_snoop_rq; -#define REG_RD_ADDR_marb_rw_no_snoop_rq 836 -#define REG_WR_ADDR_marb_rw_no_snoop_rq 836 - - -/* Constants */ -enum { - regk_marb_cpud = 0x0000000b, - regk_marb_cpui = 0x0000000a, - regk_marb_dma0 = 0x00000000, - regk_marb_dma1 = 0x00000001, - regk_marb_dma2 = 0x00000002, - regk_marb_dma3 = 0x00000003, - regk_marb_dma4 = 0x00000004, - regk_marb_dma5 = 0x00000005, - regk_marb_dma6 = 0x00000006, - regk_marb_dma7 = 0x00000007, - regk_marb_dma8 = 0x00000008, - regk_marb_dma9 = 0x00000009, - regk_marb_iop = 0x0000000c, - regk_marb_no = 0x00000000, - regk_marb_r_stopped_default = 0x00000000, - regk_marb_rw_ext_slots_default = 0x00000000, - regk_marb_rw_ext_slots_size = 0x00000040, - regk_marb_rw_int_slots_default = 0x00000000, - regk_marb_rw_int_slots_size = 0x00000040, - regk_marb_rw_intr_mask_default = 0x00000000, - regk_marb_rw_no_snoop_default = 0x00000000, - regk_marb_rw_no_snoop_rq_default = 0x00000000, - regk_marb_rw_regs_slots_default = 0x00000000, - regk_marb_rw_regs_slots_size = 0x00000004, - regk_marb_rw_stop_mask_default = 0x00000000, - regk_marb_slave = 0x0000000d, - regk_marb_yes = 0x00000001 -}; -#endif /* __marb_defs_h */ -#ifndef __marb_bp_defs_h -#define __marb_bp_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/memarb/rtl/guinness/marb_top.r - * id: <not found> - * last modfied: Mon Apr 11 16:12:16 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile marb_defs.h ../../inst/memarb/rtl/guinness/marb_top.r - * id: $Id: marb_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope marb_bp */ - -/* Register rw_first_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_first_addr; -#define REG_RD_ADDR_marb_bp_rw_first_addr 0 -#define REG_WR_ADDR_marb_bp_rw_first_addr 0 - -/* Register rw_last_addr, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_last_addr; -#define REG_RD_ADDR_marb_bp_rw_last_addr 4 -#define REG_WR_ADDR_marb_bp_rw_last_addr 4 - -/* Register rw_op, scope marb_bp, type rw */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_rw_op; -#define REG_RD_ADDR_marb_bp_rw_op 8 -#define REG_WR_ADDR_marb_bp_rw_op 8 - -/* Register rw_clients, scope marb_bp, type rw */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_rw_clients; -#define REG_RD_ADDR_marb_bp_rw_clients 12 -#define REG_WR_ADDR_marb_bp_rw_clients 12 - -/* Register rw_options, scope marb_bp, type rw */ -typedef struct { - unsigned int wrap : 1; - unsigned int dummy1 : 31; -} reg_marb_bp_rw_options; -#define REG_RD_ADDR_marb_bp_rw_options 16 -#define REG_WR_ADDR_marb_bp_rw_options 16 - -/* Register r_brk_addr, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_addr; -#define REG_RD_ADDR_marb_bp_r_brk_addr 20 - -/* Register r_brk_op, scope marb_bp, type r */ -typedef struct { - unsigned int rd : 1; - unsigned int wr : 1; - unsigned int rd_excl : 1; - unsigned int pri_wr : 1; - unsigned int us_rd : 1; - unsigned int us_wr : 1; - unsigned int us_rd_excl : 1; - unsigned int us_pri_wr : 1; - unsigned int dummy1 : 24; -} reg_marb_bp_r_brk_op; -#define REG_RD_ADDR_marb_bp_r_brk_op 24 - -/* Register r_brk_clients, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_clients; -#define REG_RD_ADDR_marb_bp_r_brk_clients 28 - -/* Register r_brk_first_client, scope marb_bp, type r */ -typedef struct { - unsigned int dma0 : 1; - unsigned int dma1 : 1; - unsigned int dma2 : 1; - unsigned int dma3 : 1; - unsigned int dma4 : 1; - unsigned int dma5 : 1; - unsigned int dma6 : 1; - unsigned int dma7 : 1; - unsigned int dma8 : 1; - unsigned int dma9 : 1; - unsigned int cpui : 1; - unsigned int cpud : 1; - unsigned int iop : 1; - unsigned int slave : 1; - unsigned int dummy1 : 18; -} reg_marb_bp_r_brk_first_client; -#define REG_RD_ADDR_marb_bp_r_brk_first_client 32 - -/* Register r_brk_size, scope marb_bp, type r */ -typedef unsigned int reg_marb_bp_r_brk_size; -#define REG_RD_ADDR_marb_bp_r_brk_size 36 - -/* Register rw_ack, scope marb_bp, type rw */ -typedef unsigned int reg_marb_bp_rw_ack; -#define REG_RD_ADDR_marb_bp_rw_ack 40 -#define REG_WR_ADDR_marb_bp_rw_ack 40 - - -/* Constants */ -enum { - regk_marb_bp_no = 0x00000000, - regk_marb_bp_rw_op_default = 0x00000000, - regk_marb_bp_rw_options_default = 0x00000000, - regk_marb_bp_yes = 0x00000001 -}; -#endif /* __marb_bp_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h deleted file mode 100644 index 0a316dc36a6b..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/pinmux_defs.h +++ /dev/null @@ -1,358 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __pinmux_defs_h -#define __pinmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: pinmux_regs.r,v 1.40 2005/02/09 16:22:59 perz Exp - * last modfied: Mon Apr 11 16:09:11 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile pinmux_defs.h ../../inst/pinmux/rtl/guinness/pinmux_regs.r - * id: $Id: pinmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope pinmux */ - -/* Register rw_pa, scope pinmux, type rw */ -typedef struct { - unsigned int pa0 : 1; - unsigned int pa1 : 1; - unsigned int pa2 : 1; - unsigned int pa3 : 1; - unsigned int pa4 : 1; - unsigned int pa5 : 1; - unsigned int pa6 : 1; - unsigned int pa7 : 1; - unsigned int csp2_n : 1; - unsigned int csp3_n : 1; - unsigned int csp5_n : 1; - unsigned int csp6_n : 1; - unsigned int hsh4 : 1; - unsigned int hsh5 : 1; - unsigned int hsh6 : 1; - unsigned int hsh7 : 1; - unsigned int dummy1 : 16; -} reg_pinmux_rw_pa; -#define REG_RD_ADDR_pinmux_rw_pa 0 -#define REG_WR_ADDR_pinmux_rw_pa 0 - -/* Register rw_hwprot, scope pinmux, type rw */ -typedef struct { - unsigned int ser1 : 1; - unsigned int ser2 : 1; - unsigned int ser3 : 1; - unsigned int sser0 : 1; - unsigned int sser1 : 1; - unsigned int ata0 : 1; - unsigned int ata1 : 1; - unsigned int ata2 : 1; - unsigned int ata3 : 1; - unsigned int ata : 1; - unsigned int eth1 : 1; - unsigned int eth1_mgm : 1; - unsigned int timer : 1; - unsigned int p21 : 1; - unsigned int dummy1 : 18; -} reg_pinmux_rw_hwprot; -#define REG_RD_ADDR_pinmux_rw_hwprot 4 -#define REG_WR_ADDR_pinmux_rw_hwprot 4 - -/* Register rw_pb_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_gio; -#define REG_RD_ADDR_pinmux_rw_pb_gio 8 -#define REG_WR_ADDR_pinmux_rw_pb_gio 8 - -/* Register rw_pb_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pb0 : 1; - unsigned int pb1 : 1; - unsigned int pb2 : 1; - unsigned int pb3 : 1; - unsigned int pb4 : 1; - unsigned int pb5 : 1; - unsigned int pb6 : 1; - unsigned int pb7 : 1; - unsigned int pb8 : 1; - unsigned int pb9 : 1; - unsigned int pb10 : 1; - unsigned int pb11 : 1; - unsigned int pb12 : 1; - unsigned int pb13 : 1; - unsigned int pb14 : 1; - unsigned int pb15 : 1; - unsigned int pb16 : 1; - unsigned int pb17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pb_iop; -#define REG_RD_ADDR_pinmux_rw_pb_iop 12 -#define REG_WR_ADDR_pinmux_rw_pb_iop 12 - -/* Register rw_pc_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_gio; -#define REG_RD_ADDR_pinmux_rw_pc_gio 16 -#define REG_WR_ADDR_pinmux_rw_pc_gio 16 - -/* Register rw_pc_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pc0 : 1; - unsigned int pc1 : 1; - unsigned int pc2 : 1; - unsigned int pc3 : 1; - unsigned int pc4 : 1; - unsigned int pc5 : 1; - unsigned int pc6 : 1; - unsigned int pc7 : 1; - unsigned int pc8 : 1; - unsigned int pc9 : 1; - unsigned int pc10 : 1; - unsigned int pc11 : 1; - unsigned int pc12 : 1; - unsigned int pc13 : 1; - unsigned int pc14 : 1; - unsigned int pc15 : 1; - unsigned int pc16 : 1; - unsigned int pc17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pc_iop; -#define REG_RD_ADDR_pinmux_rw_pc_iop 20 -#define REG_WR_ADDR_pinmux_rw_pc_iop 20 - -/* Register rw_pd_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_gio; -#define REG_RD_ADDR_pinmux_rw_pd_gio 24 -#define REG_WR_ADDR_pinmux_rw_pd_gio 24 - -/* Register rw_pd_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pd0 : 1; - unsigned int pd1 : 1; - unsigned int pd2 : 1; - unsigned int pd3 : 1; - unsigned int pd4 : 1; - unsigned int pd5 : 1; - unsigned int pd6 : 1; - unsigned int pd7 : 1; - unsigned int pd8 : 1; - unsigned int pd9 : 1; - unsigned int pd10 : 1; - unsigned int pd11 : 1; - unsigned int pd12 : 1; - unsigned int pd13 : 1; - unsigned int pd14 : 1; - unsigned int pd15 : 1; - unsigned int pd16 : 1; - unsigned int pd17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pd_iop; -#define REG_RD_ADDR_pinmux_rw_pd_iop 28 -#define REG_WR_ADDR_pinmux_rw_pd_iop 28 - -/* Register rw_pe_gio, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_gio; -#define REG_RD_ADDR_pinmux_rw_pe_gio 32 -#define REG_WR_ADDR_pinmux_rw_pe_gio 32 - -/* Register rw_pe_iop, scope pinmux, type rw */ -typedef struct { - unsigned int pe0 : 1; - unsigned int pe1 : 1; - unsigned int pe2 : 1; - unsigned int pe3 : 1; - unsigned int pe4 : 1; - unsigned int pe5 : 1; - unsigned int pe6 : 1; - unsigned int pe7 : 1; - unsigned int pe8 : 1; - unsigned int pe9 : 1; - unsigned int pe10 : 1; - unsigned int pe11 : 1; - unsigned int pe12 : 1; - unsigned int pe13 : 1; - unsigned int pe14 : 1; - unsigned int pe15 : 1; - unsigned int pe16 : 1; - unsigned int pe17 : 1; - unsigned int dummy1 : 14; -} reg_pinmux_rw_pe_iop; -#define REG_RD_ADDR_pinmux_rw_pe_iop 36 -#define REG_WR_ADDR_pinmux_rw_pe_iop 36 - -/* Register rw_usb_phy, scope pinmux, type rw */ -typedef struct { - unsigned int en_usb0 : 1; - unsigned int en_usb1 : 1; - unsigned int dummy1 : 30; -} reg_pinmux_rw_usb_phy; -#define REG_RD_ADDR_pinmux_rw_usb_phy 40 -#define REG_WR_ADDR_pinmux_rw_usb_phy 40 - - -/* Constants */ -enum { - regk_pinmux_no = 0x00000000, - regk_pinmux_rw_hwprot_default = 0x00000000, - regk_pinmux_rw_pa_default = 0x00000000, - regk_pinmux_rw_pb_gio_default = 0x00000000, - regk_pinmux_rw_pb_iop_default = 0x00000000, - regk_pinmux_rw_pc_gio_default = 0x00000000, - regk_pinmux_rw_pc_iop_default = 0x00000000, - regk_pinmux_rw_pd_gio_default = 0x00000000, - regk_pinmux_rw_pd_iop_default = 0x00000000, - regk_pinmux_rw_pe_gio_default = 0x00000000, - regk_pinmux_rw_pe_iop_default = 0x00000000, - regk_pinmux_rw_usb_phy_default = 0x00000000, - regk_pinmux_yes = 0x00000001 -}; -#endif /* __pinmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h deleted file mode 100644 index 1bfca2666158..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/reg_map.h +++ /dev/null @@ -1,105 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __reg_map_h -#define __reg_map_h - -/* - * This file is autogenerated from - * file: ../../mod/fakereg.rmap - * id: fakereg.rmap,v 1.3 2004/02/11 19:53:22 ronny Exp - * last modified: Wed Feb 11 20:53:25 2004 - * file: ../../rtl/global.rmap - * id: global.rmap,v 1.3 2003/08/18 15:08:23 mikaeln Exp - * last modified: Mon Aug 18 17:08:23 2003 - * file: ../../mod/modreg.rmap - * id: modreg.rmap,v 1.31 2004/02/20 15:40:04 stefans Exp - * last modified: Fri Feb 20 16:40:04 2004 - * - * by /n/asic/design/tools/rdesc/src/rdes2c -map -base 0xb0000000 ../../rtl/global.rmap ../../mod/modreg.rmap ../../inst/io_proc/rtl/guinness/iop_top.r ../../inst/memarb/rtl/guinness/marb_top.r ../../mod/fakereg.rmap - * id: $Id: reg_map.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -typedef enum { - regi_ata = 0xb0032000, - regi_bif_core = 0xb0014000, - regi_bif_dma = 0xb0016000, - regi_bif_slave = 0xb0018000, - regi_config = 0xb003c000, - regi_dma0 = 0xb0000000, - regi_dma1 = 0xb0002000, - regi_dma2 = 0xb0004000, - regi_dma3 = 0xb0006000, - regi_dma4 = 0xb0008000, - regi_dma5 = 0xb000a000, - regi_dma6 = 0xb000c000, - regi_dma7 = 0xb000e000, - regi_dma8 = 0xb0010000, - regi_dma9 = 0xb0012000, - regi_eth0 = 0xb0034000, - regi_eth1 = 0xb0036000, - regi_gio = 0xb001a000, - regi_iop = 0xb0020000, - regi_iop_version = 0xb0020000, - regi_iop_fifo_in0_extra = 0xb0020040, - regi_iop_fifo_in1_extra = 0xb0020080, - regi_iop_fifo_out0_extra = 0xb00200c0, - regi_iop_fifo_out1_extra = 0xb0020100, - regi_iop_trigger_grp0 = 0xb0020140, - regi_iop_trigger_grp1 = 0xb0020180, - regi_iop_trigger_grp2 = 0xb00201c0, - regi_iop_trigger_grp3 = 0xb0020200, - regi_iop_trigger_grp4 = 0xb0020240, - regi_iop_trigger_grp5 = 0xb0020280, - regi_iop_trigger_grp6 = 0xb00202c0, - regi_iop_trigger_grp7 = 0xb0020300, - regi_iop_crc_par0 = 0xb0020380, - regi_iop_crc_par1 = 0xb0020400, - regi_iop_dmc_in0 = 0xb0020480, - regi_iop_dmc_in1 = 0xb0020500, - regi_iop_dmc_out0 = 0xb0020580, - regi_iop_dmc_out1 = 0xb0020600, - regi_iop_fifo_in0 = 0xb0020680, - regi_iop_fifo_in1 = 0xb0020700, - regi_iop_fifo_out0 = 0xb0020780, - regi_iop_fifo_out1 = 0xb0020800, - regi_iop_scrc_in0 = 0xb0020880, - regi_iop_scrc_in1 = 0xb0020900, - regi_iop_scrc_out0 = 0xb0020980, - regi_iop_scrc_out1 = 0xb0020a00, - regi_iop_timer_grp0 = 0xb0020a80, - regi_iop_timer_grp1 = 0xb0020b00, - regi_iop_timer_grp2 = 0xb0020b80, - regi_iop_timer_grp3 = 0xb0020c00, - regi_iop_sap_in = 0xb0020d00, - regi_iop_sap_out = 0xb0020e00, - regi_iop_spu0 = 0xb0020f00, - regi_iop_spu1 = 0xb0021000, - regi_iop_sw_cfg = 0xb0021100, - regi_iop_sw_cpu = 0xb0021200, - regi_iop_sw_mpu = 0xb0021300, - regi_iop_sw_spu0 = 0xb0021400, - regi_iop_sw_spu1 = 0xb0021500, - regi_iop_mpu = 0xb0021600, - regi_irq = 0xb001c000, - regi_irq2 = 0xb005c000, - regi_marb = 0xb003e000, - regi_marb_bp0 = 0xb003e240, - regi_marb_bp1 = 0xb003e280, - regi_marb_bp2 = 0xb003e2c0, - regi_marb_bp3 = 0xb003e300, - regi_pinmux = 0xb0038000, - regi_ser0 = 0xb0026000, - regi_ser1 = 0xb0028000, - regi_ser2 = 0xb002a000, - regi_ser3 = 0xb002c000, - regi_sser0 = 0xb0022000, - regi_sser1 = 0xb0024000, - regi_strcop = 0xb0030000, - regi_strmux = 0xb003a000, - regi_timer = 0xb001e000, - regi_timer0 = 0xb001e000, - regi_timer2 = 0xb005e000, - regi_trace = 0xb0040000, -} reg_scope_instances; -#endif /* __reg_map_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h deleted file mode 100644 index 0ab49edb1c81..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/strmux_defs.h +++ /dev/null @@ -1,128 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __strmux_defs_h -#define __strmux_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: strmux_regs.r,v 1.10 2005/02/10 10:10:46 perz Exp - * last modfied: Mon Apr 11 16:09:43 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile strmux_defs.h ../../inst/strmux/rtl/guinness/strmux_regs.r - * id: $Id: strmux_defs.h,v 1.1 2007/02/13 11:55:30 starvik Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope strmux */ - -/* Register rw_cfg, scope strmux, type rw */ -typedef struct { - unsigned int dma0 : 3; - unsigned int dma1 : 3; - unsigned int dma2 : 3; - unsigned int dma3 : 3; - unsigned int dma4 : 3; - unsigned int dma5 : 3; - unsigned int dma6 : 3; - unsigned int dma7 : 3; - unsigned int dma8 : 3; - unsigned int dma9 : 3; - unsigned int dummy1 : 2; -} reg_strmux_rw_cfg; -#define REG_RD_ADDR_strmux_rw_cfg 0 -#define REG_WR_ADDR_strmux_rw_cfg 0 - - -/* Constants */ -enum { - regk_strmux_ata = 0x00000003, - regk_strmux_eth0 = 0x00000001, - regk_strmux_eth1 = 0x00000004, - regk_strmux_ext0 = 0x00000001, - regk_strmux_ext1 = 0x00000001, - regk_strmux_ext2 = 0x00000001, - regk_strmux_ext3 = 0x00000001, - regk_strmux_iop0 = 0x00000002, - regk_strmux_iop1 = 0x00000001, - regk_strmux_off = 0x00000000, - regk_strmux_p21 = 0x00000004, - regk_strmux_rw_cfg_default = 0x00000000, - regk_strmux_ser0 = 0x00000002, - regk_strmux_ser1 = 0x00000002, - regk_strmux_ser2 = 0x00000004, - regk_strmux_ser3 = 0x00000003, - regk_strmux_sser0 = 0x00000003, - regk_strmux_sser1 = 0x00000003, - regk_strmux_strcop = 0x00000002 -}; -#endif /* __strmux_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h b/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h deleted file mode 100644 index 59c70ba9959b..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/hwregs/timer_defs.h +++ /dev/null @@ -1,267 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef __timer_defs_h -#define __timer_defs_h - -/* - * This file is autogenerated from - * file: ../../inst/timer/rtl/timer_regs.r - * id: timer_regs.r,v 1.7 2003/03/11 11:16:59 perz Exp - * last modfied: Mon Apr 11 16:09:53 2005 - * - * by /n/asic/design/tools/rdesc/src/rdes2c --outfile timer_defs.h ../../inst/timer/rtl/timer_regs.r - * id: $Id: timer_defs.h,v 1.1 2007/04/11 13:51:01 ricardw Exp $ - * Any changes here will be lost. - * - * -*- buffer-read-only: t -*- - */ -/* Main access macros */ -#ifndef REG_RD -#define REG_RD( scope, inst, reg ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR -#define REG_WR( scope, inst, reg, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_VECT -#define REG_RD_VECT( scope, inst, reg, index ) \ - REG_READ( reg_##scope##_##reg, \ - (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_VECT -#define REG_WR_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( reg_##scope##_##reg, \ - (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT -#define REG_RD_INT( scope, inst, reg ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT -#define REG_WR_INT( scope, inst, reg, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) ) -#endif - -#ifndef REG_RD_INT_VECT -#define REG_RD_INT_VECT( scope, inst, reg, index ) \ - REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -#ifndef REG_WR_INT_VECT -#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \ - REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg, (val) ) -#endif - -#ifndef REG_TYPE_CONV -#define REG_TYPE_CONV( type, orgtype, val ) \ - ( { union { orgtype o; type n; } r; r.o = val; r.n; } ) -#endif - -#ifndef reg_page_size -#define reg_page_size 8192 -#endif - -#ifndef REG_ADDR -#define REG_ADDR( scope, inst, reg ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg ) -#endif - -#ifndef REG_ADDR_VECT -#define REG_ADDR_VECT( scope, inst, reg, index ) \ - ( (inst) + REG_RD_ADDR_##scope##_##reg + \ - (index) * STRIDE_##scope##_##reg ) -#endif - -/* C-code for register scope timer */ - -/* Register rw_tmr0_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr0_div; -#define REG_RD_ADDR_timer_rw_tmr0_div 0 -#define REG_WR_ADDR_timer_rw_tmr0_div 0 - -/* Register r_tmr0_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr0_data; -#define REG_RD_ADDR_timer_r_tmr0_data 4 - -/* Register rw_tmr0_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr0_ctrl; -#define REG_RD_ADDR_timer_rw_tmr0_ctrl 8 -#define REG_WR_ADDR_timer_rw_tmr0_ctrl 8 - -/* Register rw_tmr1_div, scope timer, type rw */ -typedef unsigned int reg_timer_rw_tmr1_div; -#define REG_RD_ADDR_timer_rw_tmr1_div 16 -#define REG_WR_ADDR_timer_rw_tmr1_div 16 - -/* Register r_tmr1_data, scope timer, type r */ -typedef unsigned int reg_timer_r_tmr1_data; -#define REG_RD_ADDR_timer_r_tmr1_data 20 - -/* Register rw_tmr1_ctrl, scope timer, type rw */ -typedef struct { - unsigned int op : 2; - unsigned int freq : 3; - unsigned int dummy1 : 27; -} reg_timer_rw_tmr1_ctrl; -#define REG_RD_ADDR_timer_rw_tmr1_ctrl 24 -#define REG_WR_ADDR_timer_rw_tmr1_ctrl 24 - -/* Register rs_cnt_data, scope timer, type rs */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_rs_cnt_data; -#define REG_RD_ADDR_timer_rs_cnt_data 32 - -/* Register r_cnt_data, scope timer, type r */ -typedef struct { - unsigned int tmr : 24; - unsigned int cnt : 8; -} reg_timer_r_cnt_data; -#define REG_RD_ADDR_timer_r_cnt_data 36 - -/* Register rw_cnt_cfg, scope timer, type rw */ -typedef struct { - unsigned int clk : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_cnt_cfg; -#define REG_RD_ADDR_timer_rw_cnt_cfg 40 -#define REG_WR_ADDR_timer_rw_cnt_cfg 40 - -/* Register rw_trig, scope timer, type rw */ -typedef unsigned int reg_timer_rw_trig; -#define REG_RD_ADDR_timer_rw_trig 48 -#define REG_WR_ADDR_timer_rw_trig 48 - -/* Register rw_trig_cfg, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_trig_cfg; -#define REG_RD_ADDR_timer_rw_trig_cfg 52 -#define REG_WR_ADDR_timer_rw_trig_cfg 52 - -/* Register r_time, scope timer, type r */ -typedef unsigned int reg_timer_r_time; -#define REG_RD_ADDR_timer_r_time 56 - -/* Register rw_out, scope timer, type rw */ -typedef struct { - unsigned int tmr : 2; - unsigned int dummy1 : 30; -} reg_timer_rw_out; -#define REG_RD_ADDR_timer_rw_out 60 -#define REG_WR_ADDR_timer_rw_out 60 - -/* Register rw_wd_ctrl, scope timer, type rw */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int key : 7; - unsigned int dummy1 : 16; -} reg_timer_rw_wd_ctrl; -#define REG_RD_ADDR_timer_rw_wd_ctrl 64 -#define REG_WR_ADDR_timer_rw_wd_ctrl 64 - -/* Register r_wd_stat, scope timer, type r */ -typedef struct { - unsigned int cnt : 8; - unsigned int cmd : 1; - unsigned int dummy1 : 23; -} reg_timer_r_wd_stat; -#define REG_RD_ADDR_timer_r_wd_stat 68 - -/* Register rw_intr_mask, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_intr_mask; -#define REG_RD_ADDR_timer_rw_intr_mask 72 -#define REG_WR_ADDR_timer_rw_intr_mask 72 - -/* Register rw_ack_intr, scope timer, type rw */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_rw_ack_intr; -#define REG_RD_ADDR_timer_rw_ack_intr 76 -#define REG_WR_ADDR_timer_rw_ack_intr 76 - -/* Register r_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_intr; -#define REG_RD_ADDR_timer_r_intr 80 - -/* Register r_masked_intr, scope timer, type r */ -typedef struct { - unsigned int tmr0 : 1; - unsigned int tmr1 : 1; - unsigned int cnt : 1; - unsigned int trig : 1; - unsigned int dummy1 : 28; -} reg_timer_r_masked_intr; -#define REG_RD_ADDR_timer_r_masked_intr 84 - -/* Register rw_test, scope timer, type rw */ -typedef struct { - unsigned int dis : 1; - unsigned int en : 1; - unsigned int dummy1 : 30; -} reg_timer_rw_test; -#define REG_RD_ADDR_timer_rw_test 88 -#define REG_WR_ADDR_timer_rw_test 88 - - -/* Constants */ -enum { - regk_timer_ext = 0x00000001, - regk_timer_f100 = 0x00000007, - regk_timer_f29_493 = 0x00000004, - regk_timer_f32 = 0x00000005, - regk_timer_f32_768 = 0x00000006, - regk_timer_hold = 0x00000001, - regk_timer_ld = 0x00000000, - regk_timer_no = 0x00000000, - regk_timer_off = 0x00000000, - regk_timer_run = 0x00000002, - regk_timer_rw_cnt_cfg_default = 0x00000000, - regk_timer_rw_intr_mask_default = 0x00000000, - regk_timer_rw_out_default = 0x00000000, - regk_timer_rw_test_default = 0x00000000, - regk_timer_rw_tmr0_ctrl_default = 0x00000000, - regk_timer_rw_tmr1_ctrl_default = 0x00000000, - regk_timer_rw_trig_cfg_default = 0x00000000, - regk_timer_start = 0x00000001, - regk_timer_stop = 0x00000000, - regk_timer_time = 0x00000001, - regk_timer_tmr0 = 0x00000002, - regk_timer_tmr1 = 0x00000003, - regk_timer_yes = 0x00000001 -}; -#endif /* __timer_defs_h */ diff --git a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h b/arch/cris/include/arch-v32/mach-fs/mach/memmap.h deleted file mode 100644 index 94328936cc91..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/memmap.h +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_ARCH_MEMMAP_H -#define _ASM_ARCH_MEMMAP_H - -#define MEM_CSE0_START (0x00000000) -#define MEM_CSE0_SIZE (0x04000000) -#define MEM_CSE1_START (0x04000000) -#define MEM_CSE1_SIZE (0x04000000) -#define MEM_CSR0_START (0x08000000) -#define MEM_CSR1_START (0x0c000000) -#define MEM_CSP0_START (0x10000000) -#define MEM_CSP1_START (0x14000000) -#define MEM_CSP2_START (0x18000000) -#define MEM_CSP3_START (0x1c000000) -#define MEM_CSP4_START (0x20000000) -#define MEM_CSP5_START (0x24000000) -#define MEM_CSP6_START (0x28000000) -#define MEM_CSP7_START (0x2c000000) -#define MEM_INTMEM_START (0x38000000) -#define MEM_INTMEM_SIZE (0x00020000) -#define MEM_DRAM_START (0x40000000) - -#define MEM_NON_CACHEABLE (0x80000000) - -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h b/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h deleted file mode 100644 index 1d87f1392dc8..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/pinmux.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_CRIS_ARCH_PINMUX_H -#define _ASM_CRIS_ARCH_PINMUX_H - -#define PORT_B 0 -#define PORT_C 1 -#define PORT_D 2 -#define PORT_E 3 - -enum pin_mode { - pinmux_none = 0, - pinmux_fixed, - pinmux_gpio, - pinmux_iop -}; - -enum fixed_function { - pinmux_ser1, - pinmux_ser2, - pinmux_ser3, - pinmux_sser0, - pinmux_sser1, - pinmux_ata0, - pinmux_ata1, - pinmux_ata2, - pinmux_ata3, - pinmux_ata, - pinmux_eth1, - pinmux_timer -}; - -int crisv32_pinmux_alloc(int port, int first_pin, int last_pin, enum pin_mode); -int crisv32_pinmux_alloc_fixed(enum fixed_function function); -int crisv32_pinmux_dealloc(int port, int first_pin, int last_pin); -int crisv32_pinmux_dealloc_fixed(enum fixed_function function); - -#endif diff --git a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc b/arch/cris/include/arch-v32/mach-fs/mach/startup.inc deleted file mode 100644 index 96c3b0fb62c1..000000000000 --- a/arch/cris/include/arch-v32/mach-fs/mach/startup.inc +++ /dev/null @@ -1,76 +0,0 @@ -#ifndef STARTUP_INC_INCLUDED -#define STARTUP_INC_INCLUDED - -#include <hwregs/asm/reg_map_asm.h> -#include <hwregs/asm/bif_core_defs_asm.h> -#include <hwregs/asm/gio_defs_asm.h> -#include <hwregs/asm/config_defs_asm.h> - - .macro GIO_INIT - move.d CONFIG_ETRAX_DEF_GIO_PA_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PA_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pa_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PB_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pb_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PC_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pc_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PD_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pd_oe), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OUT, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_dout), $r1 - move.d $r0, [$r1] - - move.d CONFIG_ETRAX_DEF_GIO_PE_OE, $r0 - move.d REG_ADDR(gio, regi_gio, rw_pe_oe), $r1 - move.d $r0, [$r1] - .endm - - .macro START_CLOCKS - move.d REG_ADDR(config, regi_config, rw_clk_ctrl), $r1 - move.d [$r1], $r0 - or.d REG_STATE(config, rw_clk_ctrl, cpu, yes) | \ - REG_STATE(config, rw_clk_ctrl, bif, yes) | \ - REG_STATE(config, rw_clk_ctrl, fix_io, yes), $r0 - move.d $r0, [$r1] - .endm - - .macro SETUP_WAIT_STATES - ;; Set up waitstates etc - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp1_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP1_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp2_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP2_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp3_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP3_CONFIG, $r1 - move.d $r1, [$r0] - move.d REG_ADDR(bif_core, regi_bif_core, rw_grp4_cfg), $r0 - move.d CONFIG_ETRAX_MEM_GRP4_CONFIG, $r1 - move.d $r1, [$r0] - .endm - -#endif |