diff options
| author | Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2022-10-25 12:22:09 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-11-25 11:39:22 +0100 |
| commit | d4a37561c8894a59a8546256425a757a27b01b3a (patch) | |
| tree | cbc56e3c721725a764634a3657e158cbed1383db /arch/microblaze/include/asm | |
| parent | 7df700afd9c4855617e9a102518bd988395eb249 (diff) | |
microblaze/PCI: Remove unused PCI Indirect ops
Remove unused variants of PCI indirect handling.
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Link: https://lore.kernel.org/r/20221025065214.4663-9-thippeswamy.havalige@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'arch/microblaze/include/asm')
| -rw-r--r-- | arch/microblaze/include/asm/pci-bridge.h | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/arch/microblaze/include/asm/pci-bridge.h b/arch/microblaze/include/asm/pci-bridge.h index 170369dcdbff..cd9ae71348a4 100644 --- a/arch/microblaze/include/asm/pci-bridge.h +++ b/arch/microblaze/include/asm/pci-bridge.h @@ -32,8 +32,6 @@ struct pci_controller { int first_busno; int last_busno; - int self_busno; - void __iomem *io_base_virt; resource_size_t io_base_phys; @@ -42,34 +40,6 @@ struct pci_controller { */ resource_size_t pci_mem_offset; - struct pci_ops *ops; - unsigned int __iomem *cfg_addr; - void __iomem *cfg_data; - - /* - * Used for variants of PCI indirect handling and possible quirks: - * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1 - * EXT_REG - provides access to PCI-e extended registers - * SURPRESS_PRIMARY_BUS - we suppress the setting of PCI_PRIMARY_BUS - * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS - * to determine which bus number to match on when generating type0 - * config cycles - * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with - * hanging if we don't have link and try to do config cycles to - * anything but the PHB. Only allow talking to the PHB if this is - * set. - * BIG_ENDIAN - cfg_addr is a big endian register - * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs - * on the PLB4. Effectively disable MRM commands by setting this. - */ -#define INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 -#define INDIRECT_TYPE_EXT_REG 0x00000002 -#define INDIRECT_TYPE_SURPRESS_PRIMARY_BUS 0x00000004 -#define INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 -#define INDIRECT_TYPE_BIG_ENDIAN 0x00000010 -#define INDIRECT_TYPE_BROKEN_MRM 0x00000020 - u32 indirect_type; - /* Currently, we limit ourselves to 1 IO range and 3 mem * ranges since the common pci_bus structure can't handle more */ @@ -91,9 +61,5 @@ static inline int isa_vaddr_is_ioport(void __iomem *address) } #endif /* CONFIG_PCI */ -extern void setup_indirect_pci(struct pci_controller *hose, - resource_size_t cfg_addr, - resource_size_t cfg_data, u32 flags); - #endif /* __KERNEL__ */ #endif /* _ASM_MICROBLAZE_PCI_BRIDGE_H */ |