diff options
| author | Arınç ÜNAL <arinc.unal@arinc9.com> | 2022-03-15 19:01:50 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2022-03-16 15:10:23 +0100 |
| commit | 7a6ee0bbab2551d7189ce0f5e625fef4d612ebea (patch) | |
| tree | ded8e6489c6d3e785f6fa5b5de450f3bca8f79f8 /arch/mips/boot/dts/ralink/Makefile | |
| parent | 5aaec657369cb94e6d94ad1c66a264070e78e2b2 (diff) | |
mips: dts: ralink: add MT7621 SoC
The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc dual-core CPU,
a 5-port 10/100/1000 switch/PHY and one RGMII.
Add the devicetrees for GB-PC1 and GB-PC2 devices which use MT7621 SoC.
Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
Link: https://lore.kernel.org/r/20220315160149.3617-1-arinc.unal@arinc9.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/mips/boot/dts/ralink/Makefile')
| -rw-r--r-- | arch/mips/boot/dts/ralink/Makefile | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/mips/boot/dts/ralink/Makefile b/arch/mips/boot/dts/ralink/Makefile index 6c26dfa0a903..11732b8c8163 100644 --- a/arch/mips/boot/dts/ralink/Makefile +++ b/arch/mips/boot/dts/ralink/Makefile @@ -6,4 +6,8 @@ dtb-$(CONFIG_DTB_MT7620A_EVAL) += mt7620a_eval.dtb dtb-$(CONFIG_DTB_OMEGA2P) += omega2p.dtb dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb +dtb-$(CONFIG_SOC_MT7621) += \ + mt7621-gnubee-gb-pc1.dtb \ + mt7621-gnubee-gb-pc2.dtb + obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) |