diff options
| author | Serge Semin <fancer.lancer@gmail.com> | 2018-07-09 16:57:13 +0300 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-07-10 10:52:13 -0700 |
| commit | ddba595b7b24ac17d553814d9d525fe4472c89e6 (patch) | |
| tree | 91ac22ad216d386f813f83887fac0500abe9d462 /arch/mips/include/asm/io.h | |
| parent | 9748e33e26c65d84a0fb09df93c963d023f90a3f (diff) | |
mips: mm: Discard ioremap_uncached_accelerated() method
Adaptive ioremap_wc() method is now available as of commit 9748e33e26c6
("mips: mm: Create UCA-based ioremap_wc() method"). We can use it to
obtain UnCached Accelerated (UCA) mappings safely on all MIPS systems,
and so we don't need the MIPS-specific ioremap_uncached_accelerated()
any longer. This macro hard-coded the UCA Cache Coherency Attribute
(CCA) in a manner that isn't safe for kernels that may run on different
CPUs, and it is also entirely unused so we can trivially remove it.
[paul.burton@mips.com:
- Reword the commit message a little.
- Remove CC stable.]
Signed-off-by: Serge Semin <fancer.lancer@gmail.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/19790/
Cc: James Hogan <jhogan@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: okaya@codeaurora.org
Cc: chenhc@lemote.com
Cc: Sergey.Semin@t-platforms.ru
Cc: linux-kernel@vger.kernel.org
Diffstat (limited to 'arch/mips/include/asm/io.h')
| -rw-r--r-- | arch/mips/include/asm/io.h | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index 01e1f62d9d12..f613d1df66c0 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -301,15 +301,11 @@ static inline void __iomem * __ioremap_mode(phys_addr_t offset, unsigned long si __ioremap_mode((offset), (size), boot_cpu_data.writecombine) /* - * These two are MIPS specific ioremap variant. ioremap_cacheable_cow - * requests a cachable mapping, ioremap_uncached_accelerated requests a - * mapping using the uncached accelerated mode which isn't supported on - * all processors. + * This is a MIPS specific ioremap variant. ioremap_cacheable_cow + * requests a cachable mapping with CWB attribute enabled. */ #define ioremap_cacheable_cow(offset, size) \ __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW) -#define ioremap_uncached_accelerated(offset, size) \ - __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED) static inline void iounmap(const volatile void __iomem *addr) { |