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authorThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-08-24 18:32:43 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2020-09-07 22:23:29 +0200
commit802b83627f54d63d3d95d0285ec9a5d80be434c0 (patch)
tree240f728d7f4923617f34fba529157606d5ac9b85 /arch/mips/include/asm/mach-ip30/war.h
parent8c2ede45edbea7e970ea6bd171fc6afbec0761b3 (diff)
MIPS: Convert R4600_V1_INDEX_ICACHEOP into a config option
Use a new config option to enable R4600 V1 index I-cacheop workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/asm/mach-ip30/war.h')
-rw-r--r--arch/mips/include/asm/mach-ip30/war.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index a1fa0c1f5300..9f5c3305674c 100644
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,7 +5,6 @@
#ifndef __ASM_MIPS_MACH_IP30_WAR_H
#define __ASM_MIPS_MACH_IP30_WAR_H
-#define R4600_V1_INDEX_ICACHEOP_WAR 0
#define R4600_V1_HIT_CACHEOP_WAR 0
#define R4600_V2_HIT_CACHEOP_WAR 0
#define BCM1250_M3_WAR 0