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authorJohn Crispin <john@phrozen.org>2016-12-20 19:12:42 +0100
committerRalf Baechle <ralf@linux-mips.org>2017-01-03 16:34:47 +0100
commit16eccef68f21b729d18573a36eef41053a5f35bd (patch)
tree7e3bfa3e085a2d833d598a81b7c02fd3b9bc62d4 /arch/mips/include/asm/mach-ralink
parent2517caf19dbfac3b39f2db5500c5fd03c4370e81 (diff)
MIPS: ralink: Add missing pinmux.
The mt7620 has a pin that can be used to generate an external reference clock. The pinmux setup was missing the definition of said pin. This patch adds it. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14898/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-ralink')
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620.h7
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index a73350b07fdf..66af4ccb5c6c 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -115,9 +115,14 @@
#define MT7620_GPIO_MODE_WDT_MASK 0x3
#define MT7620_GPIO_MODE_WDT_SHIFT 21
+#define MT7620_GPIO_MODE_MDIO 0
+#define MT7620_GPIO_MODE_MDIO_REFCLK 1
+#define MT7620_GPIO_MODE_MDIO_GPIO 2
+#define MT7620_GPIO_MODE_MDIO_MASK 0x3
+#define MT7620_GPIO_MODE_MDIO_SHIFT 7
+
#define MT7620_GPIO_MODE_I2C 0
#define MT7620_GPIO_MODE_UART1 5
-#define MT7620_GPIO_MODE_MDIO 8
#define MT7620_GPIO_MODE_RGMII1 9
#define MT7620_GPIO_MODE_RGMII2 10
#define MT7620_GPIO_MODE_SPI 11