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authorGabor Juhos <juhosg@openwrt.org>2013-08-23 08:31:30 +0200
committerRalf Baechle <ralf@linux-mips.org>2013-09-04 16:57:05 +0200
commitded1e9d727f0e7cb1cf7f243dac2a87974ae048f (patch)
tree1b642fd72fda9849b8b48d03108eaf6019c4d0ab /arch/mips/include/asm/mach-ralink
parent2b9dbb15a9d4c7b8f87f98aa770f68fb60a7b170 (diff)
MIPS: ralink: mt7620: Improve clock frequency detection
The current code assumes that the peripheral clock always runs at 40MHz which is not true in all configuration. The peripheral clock can also use the reference clock instead of the fixed 40MHz rate. If the reference clock runs at a different rate, various peripheries are behaving incorrectly. Additionally, the currectly calculated system clock is also wrong. The actual value what the code computes is the rate of the DRAM which can be different from the system clock. Add new helper functions to get the rate of the different clocks and use the correct values for the registered clock devices. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-ralink')
-rw-r--r--arch/mips/include/asm/mach-ralink/mt7620.h40
1 files changed, 32 insertions, 8 deletions
diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index 9809972ea882..6f9b24f51157 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -20,6 +20,8 @@
#define SYSC_REG_CHIP_REV 0x0c
#define SYSC_REG_SYSTEM_CONFIG0 0x10
#define SYSC_REG_SYSTEM_CONFIG1 0x14
+#define SYSC_REG_CLKCFG0 0x2c
+#define SYSC_REG_CPU_SYS_CLKCFG 0x3c
#define SYSC_REG_CPLL_CONFIG0 0x54
#define SYSC_REG_CPLL_CONFIG1 0x58
@@ -29,20 +31,42 @@
#define MT7620A_CHIP_NAME0 0x3637544d
#define MT7620A_CHIP_NAME1 0x20203032
+#define SYSCFG0_XTAL_FREQ_SEL BIT(6)
+
#define CHIP_REV_PKG_MASK 0x1
#define CHIP_REV_PKG_SHIFT 16
#define CHIP_REV_VER_MASK 0xf
#define CHIP_REV_VER_SHIFT 8
#define CHIP_REV_ECO_MASK 0xf
-#define CPLL_SW_CONFIG_SHIFT 31
-#define CPLL_SW_CONFIG_MASK 0x1
-#define CPLL_CPU_CLK_SHIFT 24
-#define CPLL_CPU_CLK_MASK 0x1
-#define CPLL_MULT_RATIO_SHIFT 16
-#define CPLL_MULT_RATIO 0x7
-#define CPLL_DIV_RATIO_SHIFT 10
-#define CPLL_DIV_RATIO 0x3
+#define CLKCFG0_PERI_CLK_SEL BIT(4)
+
+#define CPU_SYS_CLKCFG_OCP_RATIO_SHIFT 16
+#define CPU_SYS_CLKCFG_OCP_RATIO_MASK 0xf
+#define CPU_SYS_CLKCFG_OCP_RATIO_1 0 /* 1:1 (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_1_5 1 /* 1:1.5 (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_2 2 /* 1:2 */
+#define CPU_SYS_CLKCFG_OCP_RATIO_2_5 3 /* 1:2.5 (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_3 4 /* 1:3 */
+#define CPU_SYS_CLKCFG_OCP_RATIO_3_5 5 /* 1:3.5 (Reserved) */
+#define CPU_SYS_CLKCFG_OCP_RATIO_4 6 /* 1:4 */
+#define CPU_SYS_CLKCFG_OCP_RATIO_5 7 /* 1:5 */
+#define CPU_SYS_CLKCFG_OCP_RATIO_10 8 /* 1:10 */
+#define CPU_SYS_CLKCFG_CPU_FDIV_SHIFT 8
+#define CPU_SYS_CLKCFG_CPU_FDIV_MASK 0x1f
+#define CPU_SYS_CLKCFG_CPU_FFRAC_SHIFT 0
+#define CPU_SYS_CLKCFG_CPU_FFRAC_MASK 0x1f
+
+#define CPLL_CFG0_SW_CFG BIT(31)
+#define CPLL_CFG0_PLL_MULT_RATIO_SHIFT 16
+#define CPLL_CFG0_PLL_MULT_RATIO_MASK 0x7
+#define CPLL_CFG0_LC_CURFCK BIT(15)
+#define CPLL_CFG0_BYPASS_REF_CLK BIT(14)
+#define CPLL_CFG0_PLL_DIV_RATIO_SHIFT 10
+#define CPLL_CFG0_PLL_DIV_RATIO_MASK 0x3
+
+#define CPLL_CFG1_CPU_AUX1 BIT(25)
+#define CPLL_CFG1_CPU_AUX0 BIT(24)
#define SYSCFG0_DRAM_TYPE_MASK 0x3
#define SYSCFG0_DRAM_TYPE_SHIFT 4