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authorAlex Smith <alex.smith@imgtec.com>2015-07-24 16:16:12 +0100
committerRalf Baechle <ralf@linux-mips.org>2015-09-03 12:08:01 +0200
commitf1f5e414851fdb69a3200e5c15799ea4788d423e (patch)
tree8abd20f22029d1595bb09e63d2f466be1ae29edd /arch/mips/include/asm/pgtable-bits.h
parent8c172467be36f7c9591e59b647e4cd342ce2ef41 (diff)
MIPS: Use Ingenic-specific write combine attribute on all Ingenic platforms
The Ingenic-specific write combining cache attribute was defined based on CONFIG_MACH_JZ4740 and therefore not used on JZ4780. Change this to CONFIG_MACH_INGENIC so that it gets used on all Ingenic platforms. Signed-off-by: Alex Smith <alex.smith@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/10769/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/pgtable-bits.h')
-rw-r--r--arch/mips/include/asm/pgtable-bits.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h
index c28a8499aec7..002eeb224733 100644
--- a/arch/mips/include/asm/pgtable-bits.h
+++ b/arch/mips/include/asm/pgtable-bits.h
@@ -249,7 +249,7 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val)
#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */
#define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */
-#elif defined(CONFIG_MACH_JZ4740)
+#elif defined(CONFIG_MACH_INGENIC)
/* Ingenic uses the WA bit to achieve write-combine memory writes */
#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT)