diff options
| author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | 2013-12-16 11:38:00 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 23:09:18 +0100 |
| commit | a80538549957bb0e0fdce147584450be802c04e1 (patch) | |
| tree | 3f7841ba1ac873d074eebe4aea3c617c28024d61 /arch/mips/include/asm/r4kcache.h | |
| parent | 41e62b0411d84e3d92deac79b83b0bacca4b9a52 (diff) | |
MIPS: asm: r4kcache: Add protected cache operation for EVA
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Diffstat (limited to 'arch/mips/include/asm/r4kcache.h')
| -rw-r--r-- | arch/mips/include/asm/r4kcache.h | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/include/asm/r4kcache.h b/arch/mips/include/asm/r4kcache.h index 789792eeb4f1..cac279c65601 100644 --- a/arch/mips/include/asm/r4kcache.h +++ b/arch/mips/include/asm/r4kcache.h @@ -212,6 +212,20 @@ static inline void flush_scache_line(unsigned long addr) : \ : "i" (op), "r" (addr)) +#define protected_cachee_op(op,addr) \ + __asm__ __volatile__( \ + " .set push \n" \ + " .set noreorder \n" \ + " .set mips0 \n" \ + " .set eva \n" \ + "1: cachee %0, (%1) \n" \ + "2: .set pop \n" \ + " .section __ex_table,\"a\" \n" \ + " "STR(PTR)" 1b, 2b \n" \ + " .previous" \ + : \ + : "i" (op), "r" (addr)) + /* * The next two are for badland addresses like signal trampolines. */ @@ -223,7 +237,11 @@ static inline void protected_flush_icache_line(unsigned long addr) break; default: +#ifdef CONFIG_EVA + protected_cachee_op(Hit_Invalidate_I, addr); +#else protected_cache_op(Hit_Invalidate_I, addr); +#endif break; } } |