diff options
| author | Paul Burton <paul.burton@mips.com> | 2019-07-22 22:00:00 +0000 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-07-23 14:33:44 -0700 |
| commit | ccd51b9fc3bf264482dab86875754c40cbe13045 (patch) | |
| tree | 18456906baa5b00295b2517f03973700420c46e7 /arch/mips/include/asm/war.h | |
| parent | 8e96b08472e6698011d3105912031e90e7ef553f (diff) | |
MIPS: Remove unused R5432_CP0_INTERRUPT_WAR
R5432_CP0_INTERRUPT_WAR is defined as 0 for every system we support, and
so the workaround is never used. Remove the dead code.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips/include/asm/war.h')
| -rw-r--r-- | arch/mips/include/asm/war.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h index 9344e247a6c8..1eedd596a064 100644 --- a/arch/mips/include/asm/war.h +++ b/arch/mips/include/asm/war.h @@ -129,19 +129,6 @@ #endif /* - * When an interrupt happens on a CP0 register read instruction, CPU may - * lock up or read corrupted values of CP0 registers after it enters - * the exception handler. - * - * This workaround makes sure that we read a "safe" CP0 register as the - * first thing in the exception handler, which breaks one of the - * pre-conditions for this problem. - */ -#ifndef R5432_CP0_INTERRUPT_WAR -#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform -#endif - -/* * Workaround for the Sibyte M3 errata the text of which can be found at * * http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt |