diff options
| author | Paul Burton <paul.burton@mips.com> | 2019-08-31 15:40:46 +0000 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-09-03 14:20:54 +0100 |
| commit | 775b089aeffa98d5f69045d9dc4fe3aaba1bc9e1 (patch) | |
| tree | fcb3a10c600fa7bc1a0118e7f0be56d2f87d4131 /arch/mips/include/asm | |
| parent | 54e8d9f07d8a4489e6ab148c3074ff10af03d3aa (diff) | |
MIPS: tlbex: Remove cpu_has_local_ebase
The cpu_has_local_ebase macro is, confusingly, not used to indicate
whether the EBase register is local to a CPU or not. Instead it
indicates whether we want to generate the TLB refill exception vector
each time a CPU is brought online. Doing this makes little sense on any
system, since we always use the same value for EBase & thus we cannot
have different TLB refill exception handlers per CPU.
Regenerating the code is not only pointless but also can be actively
harmful, as commit 8759934e2b6b ("MIPS: Build uasm-generated code only
once to avoid CPU Hotplug problem") described. That commit introduced
cpu_has_local_ebase to disable the handler regeneration for Loongson
machines, but this is by no means a Loongson-specific problem.
Remove cpu_has_local_ebase & simply generate the TLB refill handler once
during boot, just like the rest of the TLB exception handlers.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips/include/asm')
| -rw-r--r-- | arch/mips/include/asm/cpu-features.h | 3 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-dec/cpu-feature-overrides.h | 1 | ||||
| -rw-r--r-- | arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h | 1 |
3 files changed, 0 insertions, 5 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 4e2bea8875f5..983a6a7f43a1 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -243,9 +243,6 @@ #ifndef cpu_has_pindexed_dcache #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) #endif -#ifndef cpu_has_local_ebase -#define cpu_has_local_ebase 1 -#endif /* * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors diff --git a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h index 1c11310bc8ad..00beb69bfab9 100644 --- a/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-dec/cpu-feature-overrides.h @@ -32,7 +32,6 @@ #define cpu_has_vtag_icache 0 #define cpu_has_ic_fills_f_dc 0 #define cpu_has_pindexed_dcache 0 -#define cpu_has_local_ebase 0 #define cpu_icache_snoops_remote_store 1 #define cpu_has_mips_4 0 #define cpu_has_mips_5 0 diff --git a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h index 581915ce231c..4aca25f2ff06 100644 --- a/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-loongson64/cpu-feature-overrides.h @@ -43,7 +43,6 @@ #define cpu_has_vint 0 #define cpu_has_vtag_icache 0 #define cpu_has_watch 1 -#define cpu_has_local_ebase 0 #ifdef CONFIG_CPU_LOONGSON3 #define cpu_has_wsbh 1 |