diff options
| author | Siarhei Volkau <lis8215@gmail.com> | 2023-06-04 14:26:52 +0200 |
|---|---|---|
| committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2023-06-09 09:54:17 +0200 |
| commit | 6673c2763f6f999fc32cff1833c7d4d6d35f787b (patch) | |
| tree | 4aa5c4647d327aa6dbbba9be82080a78daca5118 /arch/mips/include/uapi | |
| parent | 1e13da548fbffb807633df85a244b70caa90bdf7 (diff) | |
MIPS: uaccess: emulate Ingenic LXW/LXH/LXHU uaccess
The LXW, LXH, LXHU opcodes are part of the MXU ASE found in Ingenic
XBurst based SoCs.
While technically part of the MXU ASE, they do not touch any of the SIMD
registers, and can be used even when the MXU ASE is disabled.
This patch makes it possible to emulate unaligned access for those
instructions.
Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/include/uapi')
| -rw-r--r-- | arch/mips/include/uapi/asm/inst.h | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h index 43d1faa02933..c29dbc8c1d49 100644 --- a/arch/mips/include/uapi/asm/inst.h +++ b/arch/mips/include/uapi/asm/inst.h @@ -273,6 +273,27 @@ enum lx_func { }; /* + * func field for special2 MXU opcodes (Ingenic XBurst MXU). + */ +enum mxu_func { + /* TODO, other MXU funcs */ + mxu_lx_op = 0x28, +}; + +/* + * op field for special2 MXU LX opcodes (Ingenic XBurst MXU). + */ +enum lx_ingenic_func { + mxu_lxb_op, + mxu_lxh_op, + /* reserved */ + mxu_lxw_op = 3, + mxu_lxbu_op, + mxu_lxhu_op, + /* more reserved */ +}; + +/* * BSHFL opcodes */ enum bshfl_func { @@ -774,6 +795,17 @@ struct dsp_format { /* SPEC3 DSP format instructions */ ;)))))) }; +struct mxu_lx_format { /* SPEC2 MXU LX format instructions */ + __BITFIELD_FIELD(unsigned int opcode : 6, + __BITFIELD_FIELD(unsigned int rs : 5, + __BITFIELD_FIELD(unsigned int rt : 5, + __BITFIELD_FIELD(unsigned int rd : 5, + __BITFIELD_FIELD(unsigned int strd : 2, + __BITFIELD_FIELD(unsigned int op : 3, + __BITFIELD_FIELD(unsigned int func : 6, + ;))))))) +}; + struct spec3_format { /* SPEC3 */ __BITFIELD_FIELD(unsigned int opcode:6, __BITFIELD_FIELD(unsigned int rs:5, @@ -1125,6 +1157,7 @@ union mips_instruction { struct loongson3_lswc2_format loongson3_lswc2_format; struct loongson3_lsdc2_format loongson3_lsdc2_format; struct loongson3_lscsr_format loongson3_lscsr_format; + struct mxu_lx_format mxu_lx_format; }; union mips16e_instruction { |