diff options
| author | Paul Burton <paul.burton@mips.com> | 2018-11-08 20:14:38 +0000 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2018-11-09 10:23:19 -0800 |
| commit | 378ed6f0e3c525e3b12827e7b7fb0a078ee48a32 (patch) | |
| tree | 766bb2bdd18f7aa7fce8a9ccb428cfcad8cf2feb /arch/mips/kernel | |
| parent | 183b40f992c8f98082c4d72043ecdeba0e6a4367 (diff) | |
MIPS: Avoid using .set mips0 to restore ISA
We currently have 2 commonly used methods for switching ISA within
assembly code, then restoring the original ISA.
1) Using a pair of .set push & .set pop directives. For example:
.set push
.set mips32r2
<some_insn>
.set pop
2) Using .set mips0 to restore the ISA originally specified on the
command line. For example:
.set mips32r2
<some_insn>
.set mips0
Unfortunately method 2 does not work with nanoMIPS toolchains, where the
assembler rejects the .set mips0 directive like so:
Error: cannot change ISA from nanoMIPS to mips0
In preparation for supporting nanoMIPS builds, switch all instances of
method 2 in generic non-platform-specific code to use push & pop as in
method 1 instead. The .set push & .set pop is arguably cleaner anyway,
and if nothing else it's good to consistently use one method.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Patchwork: https://patchwork.linux-mips.org/patch/21037/
Cc: linux-mips@linux-mips.org
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/genex.S | 3 | ||||
| -rw-r--r-- | arch/mips/kernel/idle.c | 5 | ||||
| -rw-r--r-- | arch/mips/kernel/syscall.c | 6 |
3 files changed, 9 insertions, 5 deletions
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index 6c0c0d0c30bd..398b905b027d 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -652,9 +652,10 @@ isrdhwr: ori k1, _THREAD_MASK xori k1, _THREAD_MASK LONG_L v1, TI_TP_VALUE(k1) + .set push .set arch=r4000 eret - .set mips0 + .set pop #endif .set pop END(handle_ri_rdhwr) diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 046846999efd..4d335b15826e 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -101,7 +101,8 @@ static void __cpuidle au1k_wait(void) unsigned long c0status = read_c0_status() | 1; /* irqs on */ __asm__( - " .set arch=r4000 \n" + " .set push \n" + " .set arch=r4000 \n" " cache 0x14, 0(%0) \n" " cache 0x14, 32(%0) \n" " sync \n" @@ -111,7 +112,7 @@ static void __cpuidle au1k_wait(void) " nop \n" " nop \n" " nop \n" - " .set mips0 \n" + " .set pop \n" : : "r" (au1k_wait), "r" (c0status)); } diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 69c17b549fd3..41a0db08cd37 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -106,6 +106,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__ ( + " .set push \n" " .set arch=r4000 \n" " li %[err], 0 \n" "1: ll %[old], (%[addr]) \n" @@ -122,7 +123,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) " "STR(PTR)" 1b, 4b \n" " "STR(PTR)" 2b, 4b \n" " .previous \n" - " .set mips0 \n" + " .set pop \n" : [old] "=&r" (old), [err] "=&r" (err), [tmp] "=&r" (tmp) @@ -132,6 +133,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__ ( + " .set push \n" " .set "MIPS_ISA_ARCH_LEVEL" \n" " li %[err], 0 \n" "1: \n" @@ -150,7 +152,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) " "STR(PTR)" 1b, 5b \n" " "STR(PTR)" 2b, 5b \n" " .previous \n" - " .set mips0 \n" + " .set pop \n" : [old] "=&r" (old), [err] "=&r" (err), [tmp] "=&r" (tmp) |