diff options
| author | Antoine Tenart <antoine.tenart@bootlin.com> | 2019-07-24 10:17:11 +0200 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-08-24 15:17:37 +0100 |
| commit | b4742e6682d5809ddf4d0a63cb57e629e815ec63 (patch) | |
| tree | 8773e70c984f06e5ad2533d28a22bf0daacd3a61 /arch/mips | |
| parent | 048dc3abe82738567435d9caa106a20eb417b28a (diff) | |
MIPS: dts: mscc: describe the PTP ready interrupt
This patch adds a description of the PTP ready interrupt, which can be
triggered when a PTP timestamp is available on an hardware FIFO.
Signed-off-by: Antoine Tenart <antoine.tenart@bootlin.com>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: davem@davemloft.net
Cc: richardcochran@gmail.com
Cc: alexandre.belloni@bootlin.com
Cc: UNGLinuxDriver@microchip.com
Cc: ralf@linux-mips.org
Cc: jhogan@kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: thomas.petazzoni@bootlin.com
Cc: allan.nielsen@microchip.com
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/boot/dts/mscc/ocelot.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi index 1e55a778def5..797d336db54d 100644 --- a/arch/mips/boot/dts/mscc/ocelot.dtsi +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi @@ -139,8 +139,8 @@ "port2", "port3", "port4", "port5", "port6", "port7", "port8", "port9", "port10", "qsys", "ana", "s2"; - interrupts = <21 22>; - interrupt-names = "xtr", "inj"; + interrupts = <18 21 22>; + interrupt-names = "ptp_rdy", "xtr", "inj"; ethernet-ports { #address-cells = <1>; |