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authorPetr Cvek <petrcvekcz@gmail.com>2019-06-20 23:39:37 +0200
committerPaul Burton <paul.burton@mips.com>2019-06-24 14:15:04 -0700
commitba1bc0fcdeaf3bf583c1517bd2e3e29cf223c969 (patch)
tree360a769a14e66ce74cf8d09062e330964b9bbd3c /arch/mips
parent7c6747bc2e3da8abb63f69eb724006ca8276ce2d (diff)
MIPS: lantiq: Fix bitfield masking
The modification of EXIN register doesn't clean the bitfield before the writing of a new value. After a few modifications the bitfield would accumulate only '1's. Signed-off-by: Petr Cvek <petrcvekcz@gmail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: hauke@hauke-m.de Cc: john@phrozen.org Cc: linux-mips@vger.kernel.org Cc: openwrt-devel@lists.openwrt.org Cc: pakahmar@hotmail.com
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/lantiq/irq.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
index 21ccd580f8f5..35d7c5f6d159 100644
--- a/arch/mips/lantiq/irq.c
+++ b/arch/mips/lantiq/irq.c
@@ -150,8 +150,9 @@ static int ltq_eiu_settype(struct irq_data *d, unsigned int type)
if (edge)
irq_set_handler(d->hwirq, handle_edge_irq);
- ltq_eiu_w32(ltq_eiu_r32(LTQ_EIU_EXIN_C) |
- (val << (i * 4)), LTQ_EIU_EXIN_C);
+ ltq_eiu_w32((ltq_eiu_r32(LTQ_EIU_EXIN_C) &
+ (~(7 << (i * 4)))) | (val << (i * 4)),
+ LTQ_EIU_EXIN_C);
}
}