diff options
| author | Greentime Hu <greentime@andestech.com> | 2017-10-24 15:40:25 +0800 |
|---|---|---|
| committer | Greentime Hu <greentime@andestech.com> | 2018-02-22 10:44:32 +0800 |
| commit | 7de9cf474083bfbba469f72dc208f7b51747632d (patch) | |
| tree | 45e8f3f41c736e8a6abc0995aaf5ab8d86bea917 /arch/nds32/include/uapi/asm | |
| parent | 664eec400bf8f3ab4d41279d6fb674a66ff3ba94 (diff) | |
nds32: Cache and TLB routines
This patch contains cache and TLB maintenance functions.
Signed-off-by: Vincent Chen <vincentc@andestech.com>
Signed-off-by: Greentime Hu <greentime@andestech.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/nds32/include/uapi/asm')
| -rw-r--r-- | arch/nds32/include/uapi/asm/cachectl.h | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/nds32/include/uapi/asm/cachectl.h b/arch/nds32/include/uapi/asm/cachectl.h new file mode 100644 index 000000000000..4cdca9b23974 --- /dev/null +++ b/arch/nds32/include/uapi/asm/cachectl.h @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 1994, 1995, 1996 by Ralf Baechle +// Copyright (C) 2005-2017 Andes Technology Corporation +#ifndef _ASM_CACHECTL +#define _ASM_CACHECTL + +/* + * Options for cacheflush system call + */ +#define ICACHE 0 /* flush instruction cache */ +#define DCACHE 1 /* writeback and flush data cache */ +#define BCACHE 2 /* flush instruction cache + writeback and flush data cache */ + +#endif /* _ASM_CACHECTL */ |