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| author | Michael Ellerman <mpe@ellerman.id.au> | 2020-05-20 23:38:13 +1000 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-05-20 23:38:13 +1000 |
| commit | 787a2b682d18997e71efc2ae92ce158ca3e319e9 (patch) | |
| tree | 3687b6fa74d576bab27183aae7d8124517b7fbeb /arch/powerpc/kvm/book3s_hv_rmhandlers.S | |
| parent | 217ba7dccef8e811eee43003bfef24f1902f37c9 (diff) | |
| parent | b1f9be9392f090f08e4ad9e2c68963aeff03bd67 (diff) | |
Merge branch 'topic/ppc-kvm' into next
Merge our topic branch shared with the kvm-ppc tree.
This brings in one commit that touches the XIVE interrupt controller
logic across core and KVM code.
Diffstat (limited to 'arch/powerpc/kvm/book3s_hv_rmhandlers.S')
| -rw-r--r-- | arch/powerpc/kvm/book3s_hv_rmhandlers.S | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/powerpc/kvm/book3s_hv_rmhandlers.S b/arch/powerpc/kvm/book3s_hv_rmhandlers.S index 70de3325d0e9..71943892c81c 100644 --- a/arch/powerpc/kvm/book3s_hv_rmhandlers.S +++ b/arch/powerpc/kvm/book3s_hv_rmhandlers.S @@ -2907,6 +2907,11 @@ kvm_cede_exit: beq 4f li r0, 0 stb r0, VCPU_CEDED(r9) + /* + * The escalation interrupts are special as we don't EOI them. + * There is no need to use the load-after-store ordering offset + * to set PQ to 10 as we won't use StoreEOI. + */ li r6, XIVE_ESB_SET_PQ_10 b 5f 4: li r0, 1 |