diff options
| author | Athira Rajeev <atrajeev@linux.vnet.ibm.com> | 2020-11-26 11:54:43 -0500 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2020-12-04 01:01:29 +1100 |
| commit | 9a8ee52634235993273c43ef67669d8168497dd7 (patch) | |
| tree | c5986a55b5729fccec889e213e33f1ecd1a9399c /arch/powerpc/perf/power10-pmu.c | |
| parent | 1f12316394e3b241e70ed620ca846002c8ace3ec (diff) | |
powerpc/perf: Fix to update cache events with l2l3 events in power10
Export l2l3 events (PM_L2_ST_MISS and PM_L2_ST) and LLC-prefetches
(PM_L3_PF_MISS_L3) via sysfs, and also add these to list of
cache_events.
Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1606409684-1589-7-git-send-email-atrajeev@linux.vnet.ibm.com
Diffstat (limited to 'arch/powerpc/perf/power10-pmu.c')
| -rw-r--r-- | arch/powerpc/perf/power10-pmu.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/arch/powerpc/perf/power10-pmu.c b/arch/powerpc/perf/power10-pmu.c index a02da6900997..79e0206ca454 100644 --- a/arch/powerpc/perf/power10-pmu.c +++ b/arch/powerpc/perf/power10-pmu.c @@ -127,6 +127,9 @@ CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1); CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ); CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS); CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3); +CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PF_MISS_L3); +CACHE_EVENT_ATTR(LLC-store-misses, PM_L2_ST_MISS); +CACHE_EVENT_ATTR(LLC-stores, PM_L2_ST); CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL); CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL); CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS); @@ -175,6 +178,9 @@ static struct attribute *power10_events_attr[] = { CACHE_EVENT_PTR(PM_IC_PREF_REQ), CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS), CACHE_EVENT_PTR(PM_DATA_FROM_L3), + CACHE_EVENT_PTR(PM_L3_PF_MISS_L3), + CACHE_EVENT_PTR(PM_L2_ST_MISS), + CACHE_EVENT_PTR(PM_L2_ST), CACHE_EVENT_PTR(PM_BR_MPRED_CMPL), CACHE_EVENT_PTR(PM_BR_CMPL), CACHE_EVENT_PTR(PM_DTLB_MISS), @@ -460,11 +466,11 @@ static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS, }, [C(OP_WRITE)] = { - [C(RESULT_ACCESS)] = -1, - [C(RESULT_MISS)] = -1, + [C(RESULT_ACCESS)] = PM_L2_ST, + [C(RESULT_MISS)] = PM_L2_ST_MISS, }, [C(OP_PREFETCH)] = { - [C(RESULT_ACCESS)] = -1, + [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3, [C(RESULT_MISS)] = 0, }, }, |