Merge tag 'riscv-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.8

StarFive:
Key peripheral support for the jh7100 that depended on the non-standard
non-coherent DMA operations, namely mmc, sdcard and sdio wifi. This
platform has long been supported out of tree by Emil and Ubuntu etc ship
images for it, so having mainline support for a wider range of
peripherals (at last) is great.

Microchip:
The flash used by Auto Update support and the corresponding QSPI
controller are added. On publicly available Icicle kits this flash is
not usable (engineering sample silicon issues) but in the future Icicle
kits will be available that have production silicon.

T-Head:
Jisheng is busy with RL this cycle and hence T-Head appears here. The
Lichee Pi and BeagleV both grow eMMC and uSD support.

Sopgho:
Support for the Huashan Pi and the cv1812h SoC it uses. The cv1812h is
almost identical to the existing cv1800b SoC. These SoCs are intended
for use in IP camera type systems but also appear on SBCs, with the last
digit denoting the amount integrated DDR3 the device has. The difference
between the cv1812h and the existing cv180x devices appears to be the
addition of video output interfaces.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: starfive: Enable SDIO wifi on JH7100 boards
  riscv: dts: starfive: Enable SD-card on JH7100 boards
  riscv: dts: starfive: Add JH7100 MMC nodes
  riscv: dts: starfive: Add pool for coherent DMA memory on JH7100 boards
  riscv: dts: starfive: Add JH7100 cache controller
  riscv: dts: starfive: Mark the JH7100 as having non-coherent DMAs
  riscv: dts: starfive: Group tuples in interrupt properties
  riscv: dts: thead: Enable LicheePi 4A eMMC and microSD
  riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD
  riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock
  riscv: dts: microchip: add the mpfs' system controller qspi & associated flash
  riscv: dts: sophgo: add Huashan Pi board device tree
  riscv: dts: sophgo: add initial CV1812H SoC device tree
  riscv: dts: sophgo: cv18xx: Add gpio devices
  riscv: dts: sophgo: Separate compatible specific for CV1800B soc
  dt-bindings: riscv: Add SOPHGO Huashan Pi board compatibles
  dt-bindings: timer: Add SOPHGO CV1812H clint
  dt-bindings: interrupt-controller: Add SOPHGO CV1812H plic

Link: https://lore.kernel.org/r/20231221-skimmed-boxy-b78aed8afdc4@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 17 insertions, 0 deletions

diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index a6faf24f1dba..7ebce6dde6e4 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -193,6 +193,12 @@
 		mboxes = <&mbox 0>;
 	};
 
+	scbclk: mssclkclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <80000000>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -523,5 +529,16 @@
 			#mbox-cells = <1>;
 			status = "disabled";
 		};
+
+		syscontroller_qspi: spi@37020100 {
+			compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x37020100 0x0 0x100>;
+			interrupt-parent = <&plic>;
+			interrupts = <110>;
+			clocks = <&scbclk>;
+			status = "disabled";
+		};
 	};
 };