diff options
| author | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-10-21 08:22:37 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmerdabbelt@google.com> | 2021-10-21 08:22:37 -0700 |
| commit | 241527bb84674bd597113892ecf2c7ed4a410e00 (patch) | |
| tree | 9154f870ac860e376f8bde6fd4c85c4dda9030a9 /arch/riscv/boot/dts/microchip | |
| parent | 9406369ae6278532cb8d9d3cf3a8f1354662fb80 (diff) | |
| parent | 9962a066f3c1d4588d0dd876ceac2c03ef87acf3 (diff) | |
Merge tag 'riscv-sifive-dt-5.16' of git://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux into for-next
RISC-V DTS changes for v5.16
Cleanups of RISC-V SiFive and Microchip DTSes with dtschema. These are
few minor fixes to make DTSes pass the dtschema, without actual
functional effect.
* tag 'riscv-sifive-dt-5.16' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
riscv: dts: sifive: add missing compatible for plic
riscv: dts: microchip: add missing compatibles for clint and plic
riscv: dts: sifive: drop duplicated nodes and properties in sifive
riscv: dts: sifive: fix Unleashed board compatible
riscv: dts: sifive: use only generic JEDEC SPI NOR flash compatible
Diffstat (limited to 'arch/riscv/boot/dts/microchip')
| -rw-r--r-- | arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi index 923fa8f45790..c9f6d205d2ba 100644 --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -161,7 +161,7 @@ }; clint@2000000 { - compatible = "sifive,clint0"; + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; reg = <0x0 0x2000000 0x0 0xC000>; interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 @@ -172,7 +172,7 @@ plic: interrupt-controller@c000000 { #interrupt-cells = <1>; - compatible = "sifive,plic-1.0.0"; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; riscv,ndev = <186>; interrupt-controller; |