diff options
| author | Conor Dooley <conor.dooley@microchip.com> | 2024-01-22 12:19:55 +0000 |
|---|---|---|
| committer | Conor Dooley <conor.dooley@microchip.com> | 2024-02-06 14:22:29 +0000 |
| commit | 6c7353836a91b1479e6b81791cdc163fb04b4834 (patch) | |
| tree | 4aaf92ec1bfa67a63101cf16008b423ab66e0425 /arch/riscv/boot | |
| parent | 2db68ddbf33a76b5913ca281660979b4c48f1df6 (diff) | |
riscv: dts: microchip: add missing CAN bus clocks
The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a
CAN bus clock. The bus clock was omitted when the binding was written,
but is required for operation. Make up for lost time and add to the DT.
Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Diffstat (limited to 'arch/riscv/boot')
| -rw-r--r-- | arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 59fd2d4ea523..c2b334a64be5 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -422,7 +422,7 @@ can0: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; + clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <56>; status = "disabled"; @@ -431,7 +431,7 @@ can1: can@2010d000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; + clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <57>; status = "disabled"; |